diff options
author | Dave Airlie <airlied@redhat.com> | 2016-12-13 16:41:11 +1000 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:06:17 -0400 |
commit | 3a340294f7e7a784c83f9cd72f49987cc7daaced (patch) | |
tree | 5036c6e1698c5a31acba2f35bb17c8907c1a2da6 /drivers/gpu/drm/amd/display/include/dpcd_defs.h | |
parent | eaca91eea60e5b0732b7e9ab213359d75f36901f (diff) | |
download | linux-3a340294f7e7a784c83f9cd72f49987cc7daaced.tar.bz2 |
drm/amd/display: port to using drm dpcd defines
We only keep one list of these defines in the kernel, so we should use it.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/include/dpcd_defs.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/include/dpcd_defs.h | 223 |
1 files changed, 1 insertions, 222 deletions
diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index adfbd3380bd5..e6db9cee328a 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -26,223 +26,7 @@ #ifndef __DAL_DPCD_DEFS_H__ #define __DAL_DPCD_DEFS_H__ -enum dpcd_address { -/* addresses marked with 1.2 are only defined since DP 1.2 spec */ - - /* Reciever Capability Field */ - DPCD_ADDRESS_DPCD_REV = 0x00000, - DPCD_ADDRESS_MAX_LINK_RATE = 0x00001, - DPCD_ADDRESS_MAX_LANE_COUNT = 0x00002, - DPCD_ADDRESS_MAX_DOWNSPREAD = 0x00003, - DPCD_ADDRESS_NORP = 0x00004, - DPCD_ADDRESS_DOWNSTREAM_PORT_PRESENT = 0x00005, - DPCD_ADDRESS_MAIN_LINK_CHANNEL_CODING = 0x00006, - DPCD_ADDRESS_DOWNSTREAM_PORT_COUNT = 0x00007, - DPCD_ADDRESS_RECEIVE_PORT0_CAP0 = 0x00008, - DPCD_ADDRESS_RECEIVE_PORT0_CAP1 = 0x00009, - DPCD_ADDRESS_RECEIVE_PORT1_CAP0 = 0x0000A, - DPCD_ADDRESS_RECEIVE_PORT1_CAP1 = 0x0000B, - - DPCD_ADDRESS_I2C_SPEED_CNTL_CAP = 0x0000C,/*1.2*/ - DPCD_ADDRESS_EDP_CONFIG_CAP = 0x0000D,/*1.2*/ - DPCD_ADDRESS_TRAINING_AUX_RD_INTERVAL = 0x000E,/*1.2*/ - - DPCD_ADDRESS_MSTM_CAP = 0x00021,/*1.2*/ - - /* Audio Video Sync Data Feild */ - DPCD_ADDRESS_AV_GRANULARITY = 0x0023, - DPCD_ADDRESS_AUDIO_DECODE_LATENCY1 = 0x0024, - DPCD_ADDRESS_AUDIO_DECODE_LATENCY2 = 0x0025, - DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY1 = 0x0026, - DPCD_ADDRESS_AUDIO_POSTPROCESSING_LATENCY2 = 0x0027, - DPCD_ADDRESS_VIDEO_INTERLACED_LATENCY = 0x0028, - DPCD_ADDRESS_VIDEO_PROGRESSIVE_LATENCY = 0x0029, - DPCD_ADDRESS_AUDIO_DELAY_INSERT1 = 0x0002B, - DPCD_ADDRESS_AUDIO_DELAY_INSERT2 = 0x0002C, - DPCD_ADDRESS_AUDIO_DELAY_INSERT3 = 0x0002D, - - /* Audio capability */ - DPCD_ADDRESS_NUM_OF_AUDIO_ENDPOINTS = 0x00022, - - DPCD_ADDRESS_GUID_START = 0x00030,/*1.2*/ - DPCD_ADDRESS_GUID_END = 0x0003f,/*1.2*/ - - DPCD_ADDRESS_PSR_SUPPORT_VER = 0x00070, - DPCD_ADDRESS_PSR_CAPABILITY = 0x00071, - - DPCD_ADDRESS_DWN_STRM_PORT0_CAPS = 0x00080,/*1.2a*/ - - /* Link Configuration Field */ - DPCD_ADDRESS_LINK_BW_SET = 0x00100, - DPCD_ADDRESS_LANE_COUNT_SET = 0x00101, - DPCD_ADDRESS_TRAINING_PATTERN_SET = 0x00102, - DPCD_ADDRESS_LANE0_SET = 0x00103, - DPCD_ADDRESS_LANE1_SET = 0x00104, - DPCD_ADDRESS_LANE2_SET = 0x00105, - DPCD_ADDRESS_LANE3_SET = 0x00106, - DPCD_ADDRESS_DOWNSPREAD_CNTL = 0x00107, - DPCD_ADDRESS_I2C_SPEED_CNTL = 0x00109,/*1.2*/ - - DPCD_ADDRESS_EDP_CONFIG_SET = 0x0010A, - DPCD_ADDRESS_LINK_QUAL_LANE0_SET = 0x0010B, - DPCD_ADDRESS_LINK_QUAL_LANE1_SET = 0x0010C, - DPCD_ADDRESS_LINK_QUAL_LANE2_SET = 0x0010D, - DPCD_ADDRESS_LINK_QUAL_LANE3_SET = 0x0010E, - - DPCD_ADDRESS_LANE0_SET2 = 0x0010F,/*1.2*/ - DPCD_ADDRESS_LANE2_SET2 = 0x00110,/*1.2*/ - - DPCD_ADDRESS_MSTM_CNTL = 0x00111,/*1.2*/ - - DPCD_ADDRESS_PSR_ENABLE_CFG = 0x0170, - - /* Payload Table Configuration Field 1.2 */ - DPCD_ADDRESS_PAYLOAD_ALLOCATE_SET = 0x001C0, - DPCD_ADDRESS_PAYLOAD_ALLOCATE_START_TIMESLOT = 0x001C1, - DPCD_ADDRESS_PAYLOAD_ALLOCATE_TIMESLOT_COUNT = 0x001C2, - - DPCD_ADDRESS_SINK_COUNT = 0x0200, - DPCD_ADDRESS_DEVICE_SERVICE_IRQ_VECTOR = 0x0201, - - /* Link / Sink Status Field */ - DPCD_ADDRESS_LANE_01_STATUS = 0x00202, - DPCD_ADDRESS_LANE_23_STATUS = 0x00203, - DPCD_ADDRESS_LANE_ALIGN_STATUS_UPDATED = 0x0204, - DPCD_ADDRESS_SINK_STATUS = 0x0205, - - /* Adjust Request Field */ - DPCD_ADDRESS_ADJUST_REQUEST_LANE0_1 = 0x0206, - DPCD_ADDRESS_ADJUST_REQUEST_LANE2_3 = 0x0207, - DPCD_ADDRESS_ADJUST_REQUEST_POST_CURSOR2 = 0x020C, - - /* Test Request Field */ - DPCD_ADDRESS_TEST_REQUEST = 0x0218, - DPCD_ADDRESS_TEST_LINK_RATE = 0x0219, - DPCD_ADDRESS_TEST_LANE_COUNT = 0x0220, - DPCD_ADDRESS_TEST_PATTERN = 0x0221, - DPCD_ADDRESS_TEST_MISC1 = 0x0232, - - /* Phy Test Pattern Field */ - DPCD_ADDRESS_TEST_PHY_PATTERN = 0x0248, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_7_0 = 0x0250, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_15_8 = 0x0251, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_23_16 = 0x0252, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_31_24 = 0x0253, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_39_32 = 0x0254, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_47_40 = 0x0255, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_55_48 = 0x0256, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_63_56 = 0x0257, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_71_64 = 0x0258, - DPCD_ADDRESS_TEST_80BIT_CUSTOM_PATTERN_79_72 = 0x0259, - - /* Test Response Field*/ - DPCD_ADDRESS_TEST_RESPONSE = 0x0260, - - /* Audio Test Pattern Field 1.2*/ - DPCD_ADDRESS_TEST_AUDIO_MODE = 0x0271, - DPCD_ADDRESS_TEST_AUDIO_PATTERN_TYPE = 0x0272, - DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_1 = 0x0273, - DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_2 = 0x0274, - DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_3 = 0x0275, - DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_4 = 0x0276, - DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_5 = 0x0277, - DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_6 = 0x0278, - DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_7 = 0x0279, - DPCD_ADDRESS_TEST_AUDIO_PERIOD_CH_8 = 0x027A, - - /* Payload Table Status Field */ - DPCD_ADDRESS_PAYLOAD_TABLE_UPDATE_STATUS = 0x002C0,/*1.2*/ - DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT1 = 0x002C1,/*1.2*/ - DPCD_ADDRESS_VC_PAYLOAD_ID_SLOT63 = 0x002FF,/*1.2*/ - - /* Source Device Specific Field */ - DPCD_ADDRESS_SOURCE_DEVICE_ID_START = 0x0300, - DPCD_ADDRESS_SOURCE_DEVICE_ID_END = 0x0301, - DPCD_ADDRESS_AMD_INTERNAL_DEBUG_START = 0x030C, - DPCD_ADDRESS_AMD_INTERNAL_DEBUG_END = 0x030F, - DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_START = 0x0310, - DPCD_ADDRESS_SOURCE_SPECIFIC_TABLE_END = 0x037F, - DPCD_ADDRESS_SOURCE_RESERVED_START = 0x0380, - DPCD_ADDRESS_SOURCE_RESERVED_END = 0x03FF, - - /* Sink Device Specific Field */ - DPCD_ADDRESS_SINK_DEVICE_ID_START = 0x0400, - DPCD_ADDRESS_SINK_DEVICE_ID_END = 0x0402, - DPCD_ADDRESS_SINK_DEVICE_STR_START = 0x0403, - DPCD_ADDRESS_SINK_DEVICE_STR_END = 0x0408, - DPCD_ADDRESS_SINK_REVISION_START = 0x409, - DPCD_ADDRESS_SINK_REVISION_END = 0x40B, - - /* Branch Device Specific Field */ - DPCD_ADDRESS_BRANCH_DEVICE_ID_START = 0x0500, - DPCD_ADDRESS_BRANCH_DEVICE_ID_END = 0x0502, - DPCD_ADDRESS_BRANCH_DEVICE_STR_START = 0x0503, - DPCD_ADDRESS_BRANCH_DEVICE_STR_END = 0x0508, - DPCD_ADDRESS_BRANCH_REVISION_START = 0x0509, - DPCD_ADDRESS_BRANCH_REVISION_END = 0x050B, - - DPCD_ADDRESS_POWER_STATE = 0x0600, - - /* EDP related */ - DPCD_ADDRESS_EDP_REV = 0x0700, - DPCD_ADDRESS_EDP_CAPABILITY = 0x0701, - DPCD_ADDRESS_EDP_BACKLIGHT_ADJUST_CAP = 0x0702, - DPCD_ADDRESS_EDP_GENERAL_CAP2 = 0x0703, - - DPCD_ADDRESS_EDP_DISPLAY_CONTROL = 0x0720, - DPCD_ADDRESS_SUPPORTED_LINK_RATES = 0x00010, /* edp 1.4 */ - DPCD_ADDRESS_EDP_BACKLIGHT_SET = 0x0721, - DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_MSB = 0x0722, - DPCD_ADDRESS_EDP_BACKLIGHT_BRIGHTNESS_LSB = 0x0723, - DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT = 0x0724, - DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MIN = 0x0725, - DPCD_ADDRESS_EDP_PWMGEN_BIT_COUNT_CAP_MAX = 0x0726, - DPCD_ADDRESS_EDP_BACKLIGHT_CONTROL_STATUS = 0x0727, - DPCD_ADDRESS_EDP_BACKLIGHT_FREQ_SET = 0x0728, - DPCD_ADDRESS_EDP_REVERVED = 0x0729, - DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MSB = 0x072A, - DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_MID = 0x072B, - DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MIN_LSB = 0x072C, - DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MSB = 0x072D, - DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_MID = 0x072E, - DPCD_ADDRESS_EDP_BACKLIGNT_FREQ_CAP_MAX_LSB = 0x072F, - - DPCD_ADDRESS_EDP_DBC_MINIMUM_BRIGHTNESS_SET = 0x0732, - DPCD_ADDRESS_EDP_DBC_MAXIMUM_BRIGHTNESS_SET = 0x0733, - - /* Sideband MSG Buffers 1.2 */ - DPCD_ADDRESS_DOWN_REQ_START = 0x01000, - DPCD_ADDRESS_DOWN_REQ_END = 0x011ff, - - DPCD_ADDRESS_UP_REP_START = 0x01200, - DPCD_ADDRESS_UP_REP_END = 0x013ff, - - DPCD_ADDRESS_DOWN_REP_START = 0x01400, - DPCD_ADDRESS_DOWN_REP_END = 0x015ff, - - DPCD_ADDRESS_UP_REQ_START = 0x01600, - DPCD_ADDRESS_UP_REQ_END = 0x017ff, - - /* ESI (Event Status Indicator) Field 1.2 */ - DPCD_ADDRESS_SINK_COUNT_ESI = 0x02002, - DPCD_ADDRESS_DEVICE_IRQ_ESI0 = 0x02003, - DPCD_ADDRESS_DEVICE_IRQ_ESI1 = 0x02004, - /*@todo move dpcd_address_Lane01Status back here*/ - - DPCD_ADDRESS_PSR_ERROR_STATUS = 0x2006, - DPCD_ADDRESS_PSR_EVENT_STATUS = 0x2007, - DPCD_ADDRESS_PSR_SINK_STATUS = 0x2008, - DPCD_ADDRESS_PSR_DBG_REGISTER0 = 0x2009, - DPCD_ADDRESS_PSR_DBG_REGISTER1 = 0x200A, - - DPCD_ADDRESS_DP13_DPCD_REV = 0x2200, - DPCD_ADDRESS_DP13_MAX_LINK_RATE = 0x2201, - - /* Travis specific addresses */ - DPCD_ADDRESS_TRAVIS_SINK_DEV_SEL = 0x5f0, - DPCD_ADDRESS_TRAVIS_SINK_ACCESS_OFFSET = 0x5f1, - DPCD_ADDRESS_TRAVIS_SINK_ACCESS_REG = 0x5f2, -}; +#include <drm/drm_dp_helper.h> enum dpcd_revision { DPCD_REV_10 = 0x10, @@ -252,11 +36,6 @@ enum dpcd_revision { DPCD_REV_14 = 0x14 }; -enum dp_pwr_state { - DP_PWR_STATE_D0 = 1,/* direct HW translation! */ - DP_PWR_STATE_D3 -}; - /* these are the types stored at DOWNSTREAMPORT_PRESENT */ enum dpcd_downstream_port_type { DOWNSTREAM_DP = 0, |