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authorChangfeng <Changfeng.Zhu@amd.com>2020-07-09 14:52:11 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-10 17:41:25 -0400
commit64c51ea5a61a7ace40d4e904d6c5609c4a5bde7d (patch)
tree3703a80a707d5f2a1530aafce02fd37959924a16 /drivers/gpu/drm/amd/display/dc
parentc7f1daa1d62b373cdcf6817e9edb94c121c9ebd9 (diff)
downloadlinux-64c51ea5a61a7ace40d4e904d6c5609c4a5bde7d.tar.bz2
Revert "drm/amd/display: add mechanism to skip DCN init"
To avoid s3 faild at the first cycle on renoir platform, it needs to revert this patch: drm/amd/display: add mechanism to skip DCN init Signed-off-by: changfeng <Changfeng.Zhu@amd.com> Ackedy-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc.c4
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c28
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h2
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c5
4 files changed, 24 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 942ceb0f6383..4f97329d9daf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2683,7 +2683,6 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
dal_irq_service_ack(dc->res_pool->irqs, src);
}
-
void dc_set_power_state(
struct dc *dc,
enum dc_acpi_cm_power_state power_state)
@@ -2695,6 +2694,9 @@ void dc_set_power_state(
case DC_ACPI_CM_POWER_STATE_D0:
dc_resource_state_construct(dc, dc->current_state);
+ if (dc->ctx->dmub_srv)
+ dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
+
dc->hwss.init_hw(dc);
if (dc->hwss.init_sys_ctx != NULL &&
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 96532f7ba480..eea2429ac67d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -106,17 +106,29 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv)
DC_ERROR("Error waiting for DMUB idle: status=%d\n", status);
}
-bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
+void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv)
{
- struct dmub_srv *dmub;
- union dmub_fw_boot_status status;
+ struct dmub_srv *dmub = dc_dmub_srv->dmub;
+ struct dc_context *dc_ctx = dc_dmub_srv->ctx;
+ enum dmub_status status;
- if (!dc_dmub_srv || !dc_dmub_srv->dmub)
- return false;
+ for (;;) {
+ /* Wait up to a second for PHY init. */
+ status = dmub_srv_wait_for_phy_init(dmub, 1000000);
+ if (status == DMUB_STATUS_OK)
+ /* Initialization OK */
+ break;
- dmub = dc_dmub_srv->dmub;
+ DC_ERROR("DMCUB PHY init failed: status=%d\n", status);
+ ASSERT(0);
- status = dmub->hw_funcs.get_fw_status(dmub);
+ if (status != DMUB_STATUS_TIMEOUT)
+ /*
+ * Server likely initialized or we don't have
+ * DMCUB HW support - this won't end.
+ */
+ break;
- return status.bits.optimized_init_done;
+ /* Continue spinning so we don't hang the ASIC. */
+ }
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index 8bd20d0d7689..a3a09ccb6d26 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -56,6 +56,4 @@ void dc_dmub_srv_wait_idle(struct dc_dmub_srv *dc_dmub_srv);
void dc_dmub_srv_wait_phy_init(struct dc_dmub_srv *dc_dmub_srv);
-bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv);
-
#endif /* _DMUB_DC_SRV_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 6711ff908bcf..4a70e286b4fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1289,10 +1289,7 @@ void dcn10_init_hw(struct dc *dc)
if (!dcb->funcs->is_accelerated_mode(dcb))
hws->funcs.disable_vga(dc->hwseq);
- is_optimized_init_done = dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv);
-
- if (!is_optimized_init_done)
- hws->funcs.bios_golden_init(dc);
+ hws->funcs.bios_golden_init(dc);
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =