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| author | Dave Airlie <airlied@redhat.com> | 2021-09-28 17:08:21 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2021-09-28 17:08:26 +1000 |
| commit | 1e3944578b749449bd7fa6bf0bae4c3d3f5f1733 (patch) | |
| tree | d9f2f1573b23988a1e105905ecc5777a80810206 /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h | |
| parent | f602a96e025272d237a61df455b12893aa782d33 (diff) | |
| parent | 2485e2753ec896b169526e3ef7988589d1c458f5 (diff) | |
| download | linux-1e3944578b749449bd7fa6bf0bae4c3d3f5f1733.tar.bz2 | |
Merge tag 'amd-drm-next-5.16-2021-09-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.16-2021-09-27:
amdgpu:
- RAS improvements
- BACO fixes
- Yellow Carp updates
- Misc code cleanups
- Initial DP 2.0 support
- VCN priority handling
- Cyan Skillfish updates
- Rework IB handling for multimedia engine tests
- Backlight fixes
- DCN 3.1 power saving improvements
- Runtime PM fixes
- Modifier support for DCC image stores for gfx 10.3
- Hotplug fixes
- Clean up stack related warnings in display code
- DP alt mode fixes
- Display rework for better handling FP code
- Debugfs fixes
amdkfd:
- SVM fixes
- DMA map fixes
radeon:
- AGP fix
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210927212653.4575-1-alexander.deucher@amd.com
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h index f7f7e4fff0c2..d09eed7bcc4a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h @@ -41,6 +41,9 @@ struct dce_hwseq_wa { bool DEGVIDCN10_254; bool DEGVIDCN21; bool disallow_self_refresh_during_multi_plane_transition; +#if defined(CONFIG_DRM_AMD_DC_DCN) + bool dp_hpo_and_otg_sequence; +#endif }; struct hwseq_wa_state { |