diff options
| author | Fangzhi Zuo <Jerry.Zuo@amd.com> | 2021-07-26 14:23:42 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-09-01 16:55:10 -0400 |
| commit | d76b12da98dfb5e0cb0b7c3709372632b87da2e6 (patch) | |
| tree | 47584eb0d095f846bcbbd89dbe4a399f9052b41f /drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | |
| parent | 3bc8d9214679cc4dbd1dee634bd98a5996adbcfb (diff) | |
| download | linux-d76b12da98dfb5e0cb0b7c3709372632b87da2e6.tar.bz2 | |
drm/amd/display: Add DP 2.0 DCCG
HW Blocks:
+--------+ +-----+ +------+
| OPTC | | HDA | | HUBP |
+--------+ +-----+ +------+
| | |
| | |
HPO ====|==========|========|====
| | v |
| | +-----+ |
| | | APG | |
| | +-----+ |
| | | |
| v v v
| +---------------------+
| | HPO Stream Encoder |
| +---------------------+
| |
| v
| +--------------------+
| | HPO Link Encoder |
| +--------------------+
| |
v ===============|=============
v
+------------------+
| DIO Output Mux |
+------------------+
|
v
+-----+
| PHY |
+-----+
| PHYD32CLK[0]
v
+------+
| DCCG |
+------+
|
v
SYMCLK32
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 03f47f23fb65..7390baf916b5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -100,6 +100,9 @@ enum crc_selection { enum otg_out_mux_dest { OUT_MUX_DIO = 0, +#if defined(CONFIG_DRM_AMD_DC_DCN) + OUT_MUX_HPO_DP = 2, +#endif }; enum h_timing_div_mode { |