diff options
| author | George Shen <george.shen@amd.com> | 2022-10-07 12:43:26 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-11-01 11:47:50 -0400 |
| commit | 86975c34b6e2ce85b5b03f3b0a83333c97890ad7 (patch) | |
| tree | 176055af2e985469797a9a8c385e7e480d72fb61 /drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | |
| parent | cf472dbdd7204e1aaaf587df067e8e986616788b (diff) | |
| download | linux-86975c34b6e2ce85b5b03f3b0a83333c97890ad7.tar.bz2 | |
drm/amd/display: Fix DCN32 DSC delay calculation
[Why]
DCN32 DSC delay calculation had an unintentional integer division,
resulting in a mismatch against the DML spreadsheet.
[How]
Cast numerator to double before performing the division.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index ad66e241f9ae..4a3e7a5d2758 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -1746,7 +1746,7 @@ unsigned int dml32_DSCDelayRequirement(bool DSCEnabled, } DSCDelayRequirement_val = DSCDelayRequirement_val + (HTotal - HActive) * - dml_ceil(DSCDelayRequirement_val / HActive, 1); + dml_ceil((double)DSCDelayRequirement_val / HActive, 1); DSCDelayRequirement_val = DSCDelayRequirement_val * PixelClock / PixelClockBackEnd; |