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| author | Chris Park <chris.park@amd.com> | 2022-09-12 22:36:49 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-09-21 17:16:22 -0400 |
| commit | 88d4cea24049de0fa073462b24ab471ecd685d8a (patch) | |
| tree | 8e294e26cf5f11fbf6e12192b648b0586e027766 /drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c | |
| parent | 37a0bad677a76e51c5e9e53f5d9f8f4f3e77912f (diff) | |
| download | linux-88d4cea24049de0fa073462b24ab471ecd685d8a.tar.bz2 | |
drm/amd/display: Port DCN30 420 logic to DCN32
[Why]
420 modes are limited by FMT buffer width of 4096
which requires multi-pipe support in form of ODM
combine. If 420 modes have greater HActive than
4096, the DML logic should accomodate whether
it should be rejected, or ODM combine 2:1 or 4:1
is triggered accordingly.
[How]
FMT Buffer limit of 4096 in DCN32. Force ODM
combine depending on HActive and FMT Buffer limit.
Reject modes if TMDS 420 and above 4096.
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c')
0 files changed, 0 insertions, 0 deletions