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| author | Joseph Gravenor <joseph.gravenor@amd.com> | 2020-02-14 17:53:47 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-03-05 00:29:13 -0500 |
| commit | 8d8c82b6998767e7d049820f5c03db1b2defe3af (patch) | |
| tree | 84bfba126372c3dd2b7479a960ae58e9f497a666 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | |
| parent | c14b726ee0ca387931b9605405de9dddd4e76ee5 (diff) | |
| download | linux-8d8c82b6998767e7d049820f5c03db1b2defe3af.tar.bz2 | |
drm/amd/display: add worst case dcc meta pitch to fake plane
[why]
When we have single channel memory, we can not light up 2 4k displays
with a 1080p edp, because we don't have enough bw by a small margin.
this small margin comes from dcc meta being too large. We however don't
have this dcc meta when we create fake planes so, before the flip we
will not filter out the mode for 2 4k displays with a 1080p edp
[how]
Change get_default_swizzle_mode to something more general so we don't
end up with a separate function for every missing field in the fake
plane. Add a reasonable dcc meta to the fake plane when it is filled in,
so we filter out modes that don't have enough bandwidth. To do this, we
take the screen width and align it to 1024(8k 60)
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 34483853e889..8a81ae562f6e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -3027,7 +3027,7 @@ static struct dc_cap_funcs cap_funcs = { }; -enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state) +enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) { enum dc_status result = DC_OK; @@ -3053,7 +3053,7 @@ static struct resource_funcs dcn20_res_pool_funcs = { .add_stream_to_ctx = dcn20_add_stream_to_ctx, .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, - .get_default_swizzle_mode = dcn20_get_default_swizzle_mode, + .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .set_mcif_arb_params = dcn20_set_mcif_arb_params, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link |