diff options
| author | Anthony Koo <Anthony.Koo@amd.com> | 2020-01-30 16:47:45 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-02-11 11:50:18 -0500 |
| commit | 710e0cede86180ddc718cbb2ee7f7f9ba29a704a (patch) | |
| tree | 3913eec5781d2d1eab65c2606eb39be552f8c54c /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h | |
| parent | 7ba99b43be6527eb9bdbf137e6829d4ec4b871c6 (diff) | |
| download | linux-710e0cede86180ddc718cbb2ee7f7f9ba29a704a.tar.bz2 | |
drm/amd/display: Update register defines
[Why]
Some register defines are redundant or updated
[How]
Update register defines
Remove some redundant defines
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Sun peng Li <Sunpeng.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h index 3fccd5eeecbb..7bcee5894d2e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h @@ -36,26 +36,6 @@ #define BASE(seg) \ BASE_INNER(seg) -#define SR(reg_name)\ - .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ - mm ## reg_name - -#define SRI(reg_name, block, id)\ - .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ - mm ## block ## id ## _ ## reg_name - -#define SRI2(reg_name, block, id)\ - .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ - mm ## reg_name - -#define SRII(reg_name, block, id)\ - .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ - mm ## block ## id ## _ ## reg_name - -#define SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - - #define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \ SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\ |