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author | Wesley Chalmers <Wesley.Chalmers@amd.com> | 2021-05-06 14:51:20 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-08 12:20:57 -0400 |
commit | b4d56e0c508b2ad847aeff5691f67bd2a40034ec (patch) | |
tree | b485b9c55eeebcad02dab49a6af88177f35f87c6 /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | |
parent | bd4fd2510e20241a2ddce192eda2c5c3980c3575 (diff) | |
download | linux-b4d56e0c508b2ad847aeff5691f67bd2a40034ec.tar.bz2 |
drm/amd/display: Add Interface to set FIFO ERRDET SW Override
[WHY]
HW has handed down a new sequence which requires access to the FIFO
ERRDET SW Override register.
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c index 8774406120fc..5679983158e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c @@ -96,6 +96,15 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg, return; } +void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, + bool en) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, + DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0); +} + void dccg2_init(struct dccg *dccg) { } @@ -103,6 +112,7 @@ void dccg2_init(struct dccg *dccg) static const struct dccg_funcs dccg2_funcs = { .update_dpp_dto = dccg2_update_dpp_dto, .get_dccg_ref_freq = dccg2_get_dccg_ref_freq, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .dccg_init = dccg2_init }; |