diff options
| author | Taimur Hassan <syed.hassan@amd.com> | 2020-10-04 15:20:45 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-26 13:29:21 -0400 |
| commit | a47cc3ab051f963ebca820dc48e887e9a7101244 (patch) | |
| tree | 91532e3d3d0e7b34fc0fa38ef05e6d6dafa1cd6d /drivers/gpu/drm/amd/display/dc/dcn10 | |
| parent | 1db522cd03fdf692047e2317cfa16cf89bd42992 (diff) | |
| download | linux-a47cc3ab051f963ebca820dc48e887e9a7101244.tar.bz2 | |
drm/amd/display: Raise DPG height during timing synchronization
[Why]
Underflow counter increases in AGM when performing some mode switches due
to timing sync, which is a known hardware issue.
[How]
Temporarily raise DPG height during timing sync so that underflow is not
reported.
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 1 |
2 files changed, 20 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9528e3a46b28..6b141c9f521f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1847,10 +1847,20 @@ void dcn10_enable_timing_synchronization( struct pipe_ctx *grouped_pipes[]) { struct dc_context *dc_ctx = dc->ctx; - int i; + struct output_pixel_processor *opp; + struct timing_generator *tg; + int i, width, height; DC_SYNC_INFO("Setting up OTG reset trigger\n"); + for (i = 1; i < group_size; i++) { + opp = grouped_pipes[i]->stream_res.opp; + tg = grouped_pipes[i]->stream_res.tg; + tg->funcs->get_otg_active_size(tg, &width, &height); + if (opp->funcs->opp_program_dpg_dimensions) + opp->funcs->opp_program_dpg_dimensions(opp, width, 2*(height) + 1); + } + for (i = 1; i < group_size; i++) grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( grouped_pipes[i]->stream_res.tg, @@ -1867,6 +1877,14 @@ void dcn10_enable_timing_synchronization( grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( grouped_pipes[i]->stream_res.tg); + for (i = 1; i < group_size; i++) { + opp = grouped_pipes[i]->stream_res.opp; + tg = grouped_pipes[i]->stream_res.tg; + tg->funcs->get_otg_active_size(tg, &width, &height); + if (opp->funcs->opp_program_dpg_dimensions) + opp->funcs->opp_program_dpg_dimensions(opp, width, height); + } + DC_SYNC_INFO("Sync complete\n"); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index d79718fde5a6..d54d731415d7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -403,6 +403,7 @@ static const struct opp_funcs dcn10_opp_funcs = { .opp_program_stereo = opp1_program_stereo, .opp_pipe_clock_control = opp1_pipe_clock_control, .opp_set_disp_pattern_generator = NULL, + .opp_program_dpg_dimensions = NULL, .dpg_is_blanked = NULL, .opp_destroy = opp1_destroy }; |