drm/amd/display: move regamma from opp to dpp for dce

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

6 files changed, 70 insertions, 67 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index b62a7614fd28..1f18fcf52661 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -625,26 +625,26 @@ static bool dce110_set_output_transfer_func(
 	struct pipe_ctx *pipe_ctx,
 	const struct dc_stream *stream)
 {
-	struct output_pixel_processor *opp = pipe_ctx->opp;
+	struct transform *xfm = pipe_ctx->xfm;
 
-	opp->funcs->opp_power_on_regamma_lut(opp, true);
-	opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
+	xfm->funcs->opp_power_on_regamma_lut(xfm, true);
+	xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 
 	if (stream->out_transfer_func &&
 		stream->out_transfer_func->type ==
 			TF_TYPE_PREDEFINED &&
 		stream->out_transfer_func->tf ==
 			TRANSFER_FUNCTION_SRGB) {
-		opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB);
+		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 	} else if (dce110_translate_regamma_to_hw_format(
-				stream->out_transfer_func, &opp->regamma_params)) {
-			opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params);
-			opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER);
+				stream->out_transfer_func, &xfm->regamma_params)) {
+		xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
+		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 	} else {
-		opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_BYPASS);
+		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 	}
 
-	opp->funcs->opp_power_on_regamma_lut(opp, false);
+	xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 
 	return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
index 876445f14c85..c86105b8cfaf 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c
@@ -29,12 +29,12 @@
 #include "dce/dce_11_0_d.h"
 #include "dce/dce_11_0_sh_mask.h"
 
-#include "dce/dce_opp.h"
+#include "dce110_transform_v.h"
 
-static void power_on_lut(struct output_pixel_processor *opp,
+static void power_on_lut(struct transform *xfm,
 	bool power_on, bool inputgamma, bool regamma)
 {
-	uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
+	uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
 	int i;
 
 	if (power_on) {
@@ -65,10 +65,10 @@ static void power_on_lut(struct output_pixel_processor *opp,
 				COL_MAN_GAMMA_CORR_MEM_PWR_DIS);
 	}
 
-	dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value);
+	dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value);
 
 	for (i = 0; i < 3; i++) {
-		value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
+		value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
 		if (get_reg_field_value(value,
 				DCFEV_MEM_PWR_CTRL,
 				COL_MAN_INPUT_GAMMA_MEM_PWR_DIS) &&
@@ -81,11 +81,11 @@ static void power_on_lut(struct output_pixel_processor *opp,
 	}
 }
 
-static void set_bypass_input_gamma(struct dce110_opp *opp110)
+static void set_bypass_input_gamma(struct dce_transform *xfm_dce)
 {
 	uint32_t value;
 
-	value = dm_read_reg(opp110->base.ctx,
+	value = dm_read_reg(xfm_dce->base.ctx,
 			mmCOL_MAN_INPUT_GAMMA_CONTROL1);
 
 	set_reg_field_value(
@@ -94,11 +94,11 @@ static void set_bypass_input_gamma(struct dce110_opp *opp110)
 				COL_MAN_INPUT_GAMMA_CONTROL1,
 				INPUT_GAMMA_MODE);
 
-	dm_write_reg(opp110->base.ctx,
+	dm_write_reg(xfm_dce->base.ctx,
 			mmCOL_MAN_INPUT_GAMMA_CONTROL1, value);
 }
 
-static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode)
+static void configure_regamma_mode(struct dce_transform *xfm_dce, uint32_t mode)
 {
 	uint32_t value = 0;
 
@@ -108,7 +108,7 @@ static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode)
 				GAMMA_CORR_CONTROL,
 				GAMMA_CORR_MODE);
 
-	dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CONTROL, 0);
+	dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0);
 }
 
 /*
@@ -128,7 +128,7 @@ static void configure_regamma_mode(struct dce110_opp *opp110, uint32_t mode)
  *****************************************************************************
  */
 static void regamma_config_regions_and_segments(
-	struct dce110_opp *opp110, const struct pwl_params *params)
+	struct dce_transform *xfm_dce, const struct pwl_params *params)
 {
 	const struct gamma_curve *curve;
 	uint32_t value = 0;
@@ -146,7 +146,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_START_CNTL,
 			GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT);
 
-		dm_write_reg(opp110->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL,
+		dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL,
 				value);
 	}
 	{
@@ -157,7 +157,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_SLOPE_CNTL,
 			GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_SLOPE_CNTL, value);
 	}
 	{
@@ -168,7 +168,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_END_CNTL1,
 			GAMMA_CORR_CNTLA_EXP_REGION_END);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_END_CNTL1, value);
 	}
 	{
@@ -185,7 +185,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_END_CNTL2,
 			GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_END_CNTL2, value);
 	}
 
@@ -218,7 +218,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS);
 
 		dm_write_reg(
-			opp110->base.ctx,
+				xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_REGION_0_1,
 			value);
 	}
@@ -250,7 +250,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_REGION_2_3,
 			GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_REGION_2_3,
 			value);
 	}
@@ -282,7 +282,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_REGION_4_5,
 			GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_REGION_4_5,
 			value);
 	}
@@ -314,7 +314,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_REGION_6_7,
 			GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_REGION_6_7,
 			value);
 	}
@@ -346,7 +346,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_REGION_8_9,
 			GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_REGION_8_9,
 			value);
 	}
@@ -378,7 +378,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_REGION_10_11,
 			GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_REGION_10_11,
 			value);
 	}
@@ -410,7 +410,7 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_REGION_12_13,
 			GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_REGION_12_13,
 			value);
 	}
@@ -442,13 +442,13 @@ static void regamma_config_regions_and_segments(
 			GAMMA_CORR_CNTLA_REGION_14_15,
 			GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS);
 
-		dm_write_reg(opp110->base.ctx,
+		dm_write_reg(xfm_dce->base.ctx,
 			mmGAMMA_CORR_CNTLA_REGION_14_15,
 			value);
 	}
 }
 
-static void program_pwl(struct dce110_opp *opp110,
+static void program_pwl(struct dce_transform *xfm_dce,
 		const struct pwl_params *params)
 {
 	uint32_t value = 0;
@@ -459,10 +459,10 @@ static void program_pwl(struct dce110_opp *opp110,
 		GAMMA_CORR_LUT_WRITE_EN_MASK,
 		GAMMA_CORR_LUT_WRITE_EN_MASK);
 
-	dm_write_reg(opp110->base.ctx,
+	dm_write_reg(xfm_dce->base.ctx,
 		mmGAMMA_CORR_LUT_WRITE_EN_MASK, value);
 
-	dm_write_reg(opp110->base.ctx,
+	dm_write_reg(xfm_dce->base.ctx,
 		mmGAMMA_CORR_LUT_INDEX, 0);
 
 	/* Program REGAMMA_LUT_DATA */
@@ -473,15 +473,15 @@ static void program_pwl(struct dce110_opp *opp110,
 				params->rgb_resulted;
 
 		while (i != params->hw_points_num) {
-			dm_write_reg(opp110->base.ctx, addr, rgb->red_reg);
-			dm_write_reg(opp110->base.ctx, addr, rgb->green_reg);
-			dm_write_reg(opp110->base.ctx, addr, rgb->blue_reg);
+			dm_write_reg(xfm_dce->base.ctx, addr, rgb->red_reg);
+			dm_write_reg(xfm_dce->base.ctx, addr, rgb->green_reg);
+			dm_write_reg(xfm_dce->base.ctx, addr, rgb->blue_reg);
 
-			dm_write_reg(opp110->base.ctx, addr,
+			dm_write_reg(xfm_dce->base.ctx, addr,
 				rgb->delta_red_reg);
-			dm_write_reg(opp110->base.ctx, addr,
+			dm_write_reg(xfm_dce->base.ctx, addr,
 				rgb->delta_green_reg);
-			dm_write_reg(opp110->base.ctx, addr,
+			dm_write_reg(xfm_dce->base.ctx, addr,
 				rgb->delta_blue_reg);
 
 			++rgb;
@@ -491,36 +491,36 @@ static void program_pwl(struct dce110_opp *opp110,
 }
 
 bool dce110_opp_program_regamma_pwl_v(
-	struct output_pixel_processor *opp,
+	struct transform *xfm,
 	const struct pwl_params *params)
 {
-	struct dce110_opp *opp110 = TO_DCE110_OPP(opp);
+	struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
 
 	/* Setup regions */
-	regamma_config_regions_and_segments(opp110, params);
+	regamma_config_regions_and_segments(xfm_dce, params);
 
-	set_bypass_input_gamma(opp110);
+	set_bypass_input_gamma(xfm_dce);
 
 	/* Power on gamma LUT memory */
-	power_on_lut(opp, true, false, true);
+	power_on_lut(xfm, true, false, true);
 
 	/* Program PWL */
-	program_pwl(opp110, params);
+	program_pwl(xfm_dce, params);
 
 	/* program regamma config */
-	configure_regamma_mode(opp110, 1);
+	configure_regamma_mode(xfm_dce, 1);
 
 	/* Power return to auto back */
-	power_on_lut(opp, false, false, true);
+	power_on_lut(xfm, false, false, true);
 
 	return true;
 }
 
 void dce110_opp_power_on_regamma_lut_v(
-	struct output_pixel_processor *opp,
+	struct transform *xfm,
 	bool power_on)
 {
-	uint32_t value = dm_read_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL);
+	uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL);
 
 	set_reg_field_value(
 		value,
@@ -546,11 +546,11 @@ void dce110_opp_power_on_regamma_lut_v(
 		DCFEV_MEM_PWR_CTRL,
 		COL_MAN_INPUT_GAMMA_MEM_PWR_DIS);
 
-	dm_write_reg(opp->ctx, mmDCFEV_MEM_PWR_CTRL, value);
+	dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value);
 }
 
 void dce110_opp_set_regamma_mode_v(
-	struct output_pixel_processor *opp,
+	struct transform *xfm,
 	enum opp_regamma mode)
 {
 	// TODO: need to implement the function
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
index 24d9032faade..69d6a110dbc3 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
@@ -37,10 +37,7 @@
 /*****************************************/
 
 static const struct opp_funcs funcs = {
-		.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v,
-		.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v,
 		.opp_set_dyn_expansion = dce110_opp_set_dyn_expansion,
-		.opp_set_regamma_mode = dce110_opp_set_regamma_mode_v,
 		.opp_destroy = dce110_opp_destroy,
 		.opp_program_fmt = dce110_opp_program_fmt,
 		.opp_program_bit_depth_reduction =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
index 7deaa4f5c659..269c1a88d5bb 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
@@ -35,16 +35,5 @@ bool dce110_opp_v_construct(struct dce110_opp *opp110,
 /* underlay callbacks */
 
 
-bool dce110_opp_program_regamma_pwl_v(
-	struct output_pixel_processor *opp,
-	const struct pwl_params *params);
-
-void dce110_opp_power_on_regamma_lut_v(
-	struct output_pixel_processor *opp,
-	bool power_on);
-
-void dce110_opp_set_regamma_mode_v(
-	struct output_pixel_processor *opp,
-	enum opp_regamma mode);
 
 #endif /* __DC_OPP_DCE110_V_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
index f655145b3c47..c84823a40f61 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c
@@ -683,6 +683,9 @@ static const struct transform_funcs dce110_xfmv_funcs = {
 		dce110_xfmv_set_gamut_remap,
 	.opp_set_csc_default = dce110_opp_v_set_csc_default,
 	.opp_set_csc_adjustment = dce110_opp_v_set_csc_adjustment,
+	.opp_power_on_regamma_lut = dce110_opp_power_on_regamma_lut_v,
+	.opp_program_regamma_pwl = dce110_opp_program_regamma_pwl_v,
+	.opp_set_regamma_mode = dce110_opp_set_regamma_mode_v,
 	.transform_set_pixel_storage_depth =
 			dce110_xfmv_set_pixel_storage_depth,
 	.transform_get_optimal_number_of_taps =
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
index b7f8fdb392a5..eeed3b9f90f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h
@@ -41,4 +41,18 @@ void dce110_opp_v_set_csc_default(
 void dce110_opp_v_set_csc_adjustment(
 		struct transform *xfm,
 	const struct out_csc_color_matrix *tbl_entry);
+
+
+bool dce110_opp_program_regamma_pwl_v(
+	struct transform *xfm,
+	const struct pwl_params *params);
+
+void dce110_opp_power_on_regamma_lut_v(
+	struct transform *xfm,
+	bool power_on);
+
+void dce110_opp_set_regamma_mode_v(
+	struct transform *xfm,
+	enum opp_regamma mode);
+
 #endif