diff options
author | Roman Li <roman.li@amd.com> | 2022-06-28 18:30:47 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2022-07-13 20:57:05 -0400 |
commit | ee7b62e127c8cc6db24f83e5e116357649f6e41f (patch) | |
tree | 5ed597f6cb4b68c835457591dee89dc11e772bde /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | |
parent | 5439c41a80c00e993d18d1cd4407a6a82b35d963 (diff) | |
download | linux-ee7b62e127c8cc6db24f83e5e116357649f6e41f.tar.bz2 |
drm/amd/display: Enable DCN314 in DC
Add support for DCN 3.1.4 in Display Core
Signed-off-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index e0c390fcc12c..aaf33c79b09b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -157,13 +157,16 @@ SRII(PIXEL_RATE_CNTL, OTG, 0),\ SRII(PIXEL_RATE_CNTL, OTG, 1) - #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) +#define CS_COMMON_MASK_SH_LIST_DCN3_1_4(mask_sh)\ + CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\ + CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh), + #define CS_COMMON_MASK_SH_LIST_DCN3_2(mask_sh)\ CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh),\ CS_SF(OTG0_PIXEL_RATE_CNTL, PIPE0_DTO_SRC_SEL, mask_sh) |