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| author | Harry Wentland <harry.wentland@amd.com> | 2019-02-25 13:26:34 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:07 -0500 |
| commit | 97bda0322b8a91aa8d534763e709571b2334e585 (patch) | |
| tree | 9e572c249b54a91c58a771d5eeef5ffc51cfe587 /drivers/gpu/drm/amd/display/dc/dc_hw_types.h | |
| parent | b4f199c7b00c87183f10c0a8f635f26ba2ede3eb (diff) | |
| download | linux-97bda0322b8a91aa8d534763e709571b2334e585.tar.bz2 | |
drm/amd/display: Add DSC support for Navi (v2)
Add support for DCN2 DSC (Display Stream Compression)
HW Blocks:
+--------++------+ +----------+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+--------++------+ +----------+
| ^
v |
+--------+ +--------+
| DPP | | DWB |
+--------+ +--------+
|
v ^
+--------+ |
| MPC | |
+--------+ |
| |
v |
+-------+ +-------+ |
| OPP | <--> | DSC | |
+-------+ +-------+ |
| |
v |
+--------+ /
| OPTC | --------------
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
v2: rebase (Alex)
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_hw_types.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 6a9670de38f3..ea7a1c9efca8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -709,6 +709,9 @@ struct dc_crtc_timing_flags { * rates less than or equal to 340Mcsc */ uint32_t LTE_340MCSC_SCRAMBLE:1; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + uint32_t DSC : 1; /* Use DSC with this timing */ +#endif }; enum dc_timing_3d_format { @@ -755,6 +758,18 @@ struct dc_crtc_timing_adjust { uint32_t v_total_max; }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +struct dc_dsc_config { + uint32_t num_slices_h; /* Number of DSC slices - horizontal */ + uint32_t num_slices_v; /* Number of DSC slices - vertical */ + uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */ + bool block_pred_enable; /* DSC block prediction enable */ + uint32_t linebuf_depth; /* DSC line buffer depth */ + uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ + bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ + int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ +}; +#endif struct dc_crtc_timing { uint32_t h_total; uint32_t h_border_left; @@ -781,6 +796,9 @@ struct dc_crtc_timing { enum scanning_type scan_type; struct dc_crtc_timing_flags flags; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct dc_dsc_config dsc_cfg; +#endif }; /* Passed on init */ |