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authorIswara Nagulendran <Iswara.Nagulendran@amd.com>2022-08-19 14:10:08 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-08-29 17:59:17 -0400
commit4b91ac9e389d177e8f1af5d4499c6025e866c850 (patch)
tree36b9a6f8c97747043b8bea09ffe12b104f71a3f1 /drivers/gpu/drm/amd/display/dc/core/dc_link.c
parentb1bdb5ebb06ead49456ae9f23a12c7028076f9cb (diff)
downloadlinux-4b91ac9e389d177e8f1af5d4499c6025e866c850.tar.bz2
drm/amd/display: Fix primary EDP link detection
[HOW&WHY] EDP link detection must be updated to support a primary EDP with a link index of greater than 0. * SWDEV-342936 - dc: DSC bringup for SAG 1.5 [WHY] SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5) requires seamless switching between GPUs with DSC enabled. [HOW] Moved DSC programming to apply_single_control_ctx_to_hw before the stream enablement logic to ensure the CRC checker provides valid values for non-black frames allowing the system to come out of forced PSR on d2i. Added additional logic to both generate a black frame through setVisibility calls and keep track of the CRCs values for this black frame when coming out of forced PSR. Updating logic for DalRegKey_DisableDSC to disable DSC on EDP and all ports for systems. [CLEANED] dc: Moved DSC programming to before stream enablement [HOW&WHY] Moved DSC programming to apply_single_control_ctx_to_hw before the stream enablement logic. Co-authored-by: sregolui <sregolui@amd.com> Reviewed-by: Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by: Harry Vanzylldejong <Harry.Vanzylldejong@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: sregolui <sregolui@amd.com> Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_link.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link.c12
1 files changed, 0 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 74db87f3dc6f..38fa63d43ad9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -4303,18 +4303,6 @@ void core_link_enable_stream(
if (pipe_ctx->stream->dpms_off)
return;
- /* Have to setup DSC before DIG FE and BE are connected (which happens before the
- * link training). This is to make sure the bandwidth sent to DIG BE won't be
- * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
- * will be automatically set at a later time when the video is enabled
- * (DP_VID_STREAM_EN = 1).
- */
- if (pipe_ctx->stream->timing.flags.DSC) {
- if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
- dc_is_virtual_signal(pipe_ctx->stream->signal))
- dp_set_dsc_enable(pipe_ctx, true);
- }
-
status = enable_link(state, pipe_ctx);
if (status != DC_OK) {