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authorLeo (Hanghong) Ma <hanghong.ma@amd.com>2021-10-01 22:36:18 +0800
committerAlex Deucher <alexander.deucher@amd.com>2021-10-06 15:50:15 -0400
commit1445d967fb915156aed0e79ca80c239cb2d414ce (patch)
tree32ec60d6961f6695d47f04a58cdd1f435d113248 /drivers/gpu/drm/amd/display/dc/core/dc_link.c
parent99cc8774f7ac922a23707416e1779c4257f2d282 (diff)
downloadlinux-1445d967fb915156aed0e79ca80c239cb2d414ce.tar.bz2
drm/amd/display: Add helper for blanking all dp displays
[Why & How] The codes to blank all dp display have been called many times, so add a helper in dc_link to make it more concise. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core/dc_link.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link.c45
1 files changed, 45 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 02c7a18c095f..74da226efffe 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1906,6 +1906,51 @@ static enum dc_status enable_link_dp_mst(
return enable_link_dp(state, pipe_ctx);
}
+void blank_all_dp_displays(struct dc *dc, bool hw_init)
+{
+ unsigned int i, j, fe;
+ uint8_t dpcd_power_state = '\0';
+ enum dc_status status = DC_ERROR_UNEXPECTED;
+
+ for (i = 0; i < dc->link_count; i++) {
+ enum signal_type signal = dc->links[i]->connector_signal;
+
+ if ((signal == SIGNAL_TYPE_EDP) ||
+ (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
+ if (hw_init && signal != SIGNAL_TYPE_EDP) {
+ /* DP 2.0 spec requires that we read LTTPR caps first */
+ dp_retrieve_lttpr_cap(dc->links[i]);
+ /* if any of the displays are lit up turn them off */
+ status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+ &dpcd_power_state, sizeof(dpcd_power_state));
+ }
+
+ if ((signal != SIGNAL_TYPE_EDP && status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) ||
+ (!hw_init && dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
+ if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY &&
+ dc->links[i]->link_enc->funcs->get_dig_frontend) {
+ fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
+ if (fe == ENGINE_ID_UNKNOWN)
+ continue;
+
+ for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+ if (fe == dc->res_pool->stream_enc[j]->id) {
+ dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
+ dc->res_pool->stream_enc[j]);
+ break;
+ }
+ }
+ }
+
+ if (!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
+ (hw_init && signal != SIGNAL_TYPE_EDP))
+ dp_receiver_power_ctrl(dc->links[i], false);
+ }
+ }
+ }
+
+}
+
static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
enum engine_id eng_id,
struct ext_hdmi_settings *settings)