diff options
| author | Qingqing Zhuo <qingqing.zhuo@amd.com> | 2021-08-17 16:29:07 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-09-14 15:57:10 -0400 |
| commit | 2a50edbf10c8c56e930bfb53d8f9f00a33fd837e (patch) | |
| tree | 99f27ae2ace3521ac8e31b8a55bd61d3ed1d50dc /drivers/gpu/drm/amd/display/dc/clk_mgr | |
| parent | d020970959169627d59a711769f8c4b87bf5f90c (diff) | |
| download | linux-2a50edbf10c8c56e930bfb53d8f9f00a33fd837e.tar.bz2 | |
drm/amd/display: Apply w/a for hard hang on HPD
[Why]
HPD disable and enable sequences are not mutually exclusive
on Linux. For HPDs that spans under 1s (i.e. HPD low = 1s),
part of the disable sequence (specifically, a request to SMU
to lower refclk) could come right before the call to PHY
enablement, causing DMUB to access an irresponsive PHY
and thus a hard hang on the system.
[How]
Disable 48mhz refclk off when there is any HPD status in
connected state.
Reviewed-by: Hersen Wu <hersenwu@amd.com>
Acked-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/clk_mgr')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index c6f494f0dcea..3fabf32a0558 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -42,6 +42,7 @@ #include "clk/clk_10_0_2_sh_mask.h" #include "renoir_ip_offset.h" +#include "irq/dcn21/irq_service_dcn21.h" /* Constants */ @@ -129,9 +130,11 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; struct dc *dc = clk_mgr_base->ctx->dc; int display_count; + int irq_src; bool update_dppclk = false; bool update_dispclk = false; bool dpp_clock_lowered = false; + uint32_t hpd_state; struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; @@ -147,8 +150,15 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base, if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { display_count = rn_get_active_display_cnt_wa(dc, context); + + for (irq_src = DC_IRQ_SOURCE_HPD1; irq_src <= DC_IRQ_SOURCE_HPD5; irq_src++) { + hpd_state = dal_get_hpd_state_dcn21(dc->res_pool->irqs, irq_src); + if (hpd_state) + break; + } + /* if we can go lower, go lower */ - if (display_count == 0) { + if (display_count == 0 && !hpd_state) { rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); /* update power state */ clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; |