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authorNicholas Kazlauskas <nicholas.kazlauskas@amd.com>2018-07-24 13:19:49 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-08-27 11:09:49 -0500
commit4e60536d093f486229bb8d86c739e8ef6446df85 (patch)
tree957a153a089efa40e9c42386fb201cda08521bbb /drivers/gpu/drm/amd/display/dc/bios
parent2cb3bcdb33c0a18b25a23e7081de8c9a1698a80e (diff)
downloadlinux-4e60536d093f486229bb8d86c739e8ef6446df85.tar.bz2
drm/amd/display: Set DFS bypass flags for dce110
[Why] While there is support for using and quering DFS bypass clocks the hardware is never notified to enter DFS bypass mode for dce110. [How] Add a flag that can be set when programming the display engine PLL to enable DFS bypass mode. If this flag is set then the hardware is notified to enter DFS bypass mode and the correct display engine clock frequency can be acquired. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/bios')
-rw-r--r--drivers/gpu/drm/amd/display/dc/bios/command_table.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index a558bfaa0c46..2bd7cd97e00d 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -2201,6 +2201,9 @@ static enum bp_result program_clock_v6(
if (bp_params->flags.SET_EXTERNAL_REF_DIV_SRC)
params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
+ if (bp_params->flags.SET_DISPCLK_DFS_BYPASS)
+ params.sPCLKInput.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS;
+
if (EXEC_BIOS_CMD_TABLE(SetPixelClock, params)) {
/* True display clock is returned by VBIOS if DFS bypass
* is enabled. */