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authorTony Cheng <tony.cheng@amd.com>2017-01-14 20:56:08 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 17:10:34 -0400
commit5e701406ed446a79787feede65c81b8d3cfbdfb8 (patch)
tree165ccf59fe0cd3790ed07b74e6a4257f49c50562 /drivers/gpu/drm/amd/display/dc/bios/command_table.c
parenta10eadfb152960a760c4f52c42607d27cb3f1543 (diff)
downloadlinux-5e701406ed446a79787feede65c81b8d3cfbdfb8.tar.bz2
drm/amd/display: remove dead code
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/bios/command_table.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/bios/command_table.c114
1 files changed, 0 insertions, 114 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index 88aaf53cb8c4..3f7b2dabc2b0 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -54,12 +54,10 @@ static void init_enable_spread_spectrum_on_ppll(struct bios_parser *bp);
static void init_adjust_display_pll(struct bios_parser *bp);
static void init_dac_encoder_control(struct bios_parser *bp);
static void init_dac_output_control(struct bios_parser *bp);
-static void init_blank_crtc(struct bios_parser *bp);
static void init_set_crtc_timing(struct bios_parser *bp);
static void init_select_crtc_source(struct bios_parser *bp);
static void init_enable_crtc(struct bios_parser *bp);
static void init_enable_crtc_mem_req(struct bios_parser *bp);
-static void init_compute_memore_engine_pll(struct bios_parser *bp);
static void init_external_encoder_control(struct bios_parser *bp);
static void init_enable_disp_power_gating(struct bios_parser *bp);
static void init_program_clock(struct bios_parser *bp);
@@ -74,13 +72,11 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
init_adjust_display_pll(bp);
init_dac_encoder_control(bp);
init_dac_output_control(bp);
- init_blank_crtc(bp);
init_set_crtc_timing(bp);
init_select_crtc_source(bp);
init_enable_crtc(bp);
init_enable_crtc_mem_req(bp);
init_program_clock(bp);
- init_compute_memore_engine_pll(bp);
init_external_encoder_control(bp);
init_enable_disp_power_gating(bp);
init_set_dce_clock(bp);
@@ -1676,66 +1672,6 @@ static enum bp_result dac2_output_control_v1(
/*******************************************************************************
********************************************************************************
**
- ** BLANK CRTC
- **
- ********************************************************************************
- *******************************************************************************/
-
-static enum bp_result blank_crtc_v1(
- struct bios_parser *bp,
- struct bp_blank_crtc_parameters *bp_params,
- bool blank);
-
-static void init_blank_crtc(struct bios_parser *bp)
-{
- switch (BIOS_CMD_TABLE_PARA_REVISION(BlankCRTC)) {
- case 1:
- bp->cmd_tbl.blank_crtc = blank_crtc_v1;
- break;
- default:
- bp->cmd_tbl.blank_crtc = NULL;
- break;
- }
-}
-
-static enum bp_result blank_crtc_v1(
- struct bios_parser *bp,
- struct bp_blank_crtc_parameters *bp_params,
- bool blank)
-{
- enum bp_result result = BP_RESULT_FAILURE;
- BLANK_CRTC_PARAMETERS params = {0};
- uint8_t atom_controller_id;
-
- if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
- &atom_controller_id)) {
- params.ucCRTC = (uint8_t)atom_controller_id;
-
- if (blank)
- params.ucBlanking = ATOM_BLANKING;
- else
- params.ucBlanking = ATOM_BLANKING_OFF;
- params.usBlackColorRCr =
- cpu_to_le16((uint16_t)bp_params->black_color_rcr);
- params.usBlackColorGY =
- cpu_to_le16((uint16_t)bp_params->black_color_gy);
- params.usBlackColorBCb =
- cpu_to_le16((uint16_t)bp_params->black_color_bcb);
-
- if (EXEC_BIOS_CMD_TABLE(BlankCRTC, params))
- result = BP_RESULT_OK;
- } else
- /* Not support more than two CRTC as current ASIC, update this
- * if needed.
- */
- result = BP_RESULT_BADINPUT;
-
- return result;
-}
-
-/*******************************************************************************
- ********************************************************************************
- **
** SET CRTC TIMING
**
********************************************************************************
@@ -2242,56 +2178,6 @@ static enum bp_result program_clock_v6(
/*******************************************************************************
********************************************************************************
**
- ** COMPUTE MEMORY ENGINE PLL
- **
- ********************************************************************************
- *******************************************************************************/
-
-static enum bp_result compute_memore_engine_pll_v4(
- struct bios_parser *bp,
- struct bp_display_clock_parameters *bp_params);
-
-static void init_compute_memore_engine_pll(struct bios_parser *bp)
-{
- switch (BIOS_CMD_TABLE_PARA_REVISION(ComputeMemoryEnginePLL)) {
- case 4:
- bp->cmd_tbl.compute_memore_engine_pll =
- compute_memore_engine_pll_v4;
- break;
- default:
- bp->cmd_tbl.compute_memore_engine_pll = NULL;
- break;
- }
-}
-
-static enum bp_result compute_memore_engine_pll_v4(
- struct bios_parser *bp,
- struct bp_display_clock_parameters *bp_params)
-{
- enum bp_result result = BP_RESULT_FAILURE;
- COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 params;
-
- memset(&params, 0, sizeof(params));
-
- params.ulClock = cpu_to_le32(bp_params->target_display_clock / 10);
-
- /* Initialize this to the target clock in case this call fails */
- bp_params->actual_display_clock = bp_params->target_display_clock;
-
- if (EXEC_BIOS_CMD_TABLE(ComputeMemoryEnginePLL, params)) {
- /* Convert from 10KHz units back to KHz */
- bp_params->actual_display_clock =
- le32_to_cpu(params.ulClock) * 10;
- bp_params->actual_post_divider_id = params.ucPostDiv;
- result = BP_RESULT_OK;
- }
-
- return result;
-}
-
-/*******************************************************************************
- ********************************************************************************
- **
** EXTERNAL ENCODER CONTROL
**
********************************************************************************