summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
diff options
context:
space:
mode:
authorhersen wu <hersenxs.wu@amd.com>2022-05-29 12:12:32 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-06-21 18:17:23 -0400
commitf04d275d94e164d24516c32437c988a323018f63 (patch)
treeb140d57f1e5060356316ecf285b8dcab081bf54e /drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
parentec457f8378901d673b841e81d289b0165286db7f (diff)
downloadlinux-f04d275d94e164d24516c32437c988a323018f63.tar.bz2
drm/amd/display: add mst port output bw check
[Why] when connect one 4k@144hz dp to dsc mst hub, 4k@144hz mode is in valid mode list. but some mst hub port output bandwidth does not support 4k@144hz. [How] add mst port output bandwidth checks, include full_pbn, branch max throughput mps. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Jerry Zuo <Jerry.Zuo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c')
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 26f733b2faa0..f3ce37664143 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1353,4 +1353,40 @@ clean_exit:
return (ret == 0);
}
+
#endif
+
+enum dc_status dm_dp_mst_is_port_support_mode(
+ struct amdgpu_dm_connector *aconnector,
+ struct dc_stream_state *stream)
+{
+ int bpp, pbn, branch_max_throughput_mps = 0;
+
+ /* check if mode could be supported within fUll_pbn */
+ bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+ if (pbn > aconnector->port->full_pbn)
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+
+ /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
+ switch (stream->timing.pixel_encoding) {
+ case PIXEL_ENCODING_RGB:
+ case PIXEL_ENCODING_YCBCR444:
+ branch_max_throughput_mps =
+ aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
+ break;
+ case PIXEL_ENCODING_YCBCR422:
+ case PIXEL_ENCODING_YCBCR420:
+ branch_max_throughput_mps =
+ aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
+ break;
+ default:
+ break;
+ }
+
+ if (branch_max_throughput_mps != 0 &&
+ ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000))
+ return DC_FAIL_BANDWIDTH_VALIDATE;
+
+ return DC_OK;
+}