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| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2018-06-08 18:10:57 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-21 18:59:24 -0500 |
| commit | e0d076574e8d904fdd3334ceb04fe1bb9cb5f5c0 (patch) | |
| tree | 2a91378d6e517a64b0105544db92971229d617c7 /drivers/gpu/drm/amd/amdgpu/soc15.c | |
| parent | 6bdadb2072243154e6441bfd789dce1fc941976c (diff) | |
| download | linux-e0d076574e8d904fdd3334ceb04fe1bb9cb5f5c0.tar.bz2 | |
drm/amdgpu: update golden setting programming logic
Since from soc15, make sure only AndMasked bit get changed
when applied or_mask
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 4eb615d6dc84..fa9c27d63504 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -378,7 +378,7 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, } else { tmp = RREG32(reg); tmp &= ~(entry->and_mask); - tmp |= entry->or_mask; + tmp |= (entry->or_mask & entry->and_mask); } if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || |