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| author | Oak Zeng <Oak.Zeng@amd.com> | 2021-01-23 11:34:45 -0600 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-23 22:58:27 -0400 |
| commit | 1f928f51593ca07e2b125ca862fcff687e9e498b (patch) | |
| tree | bff7e672ae0dabcbada22c9861bd69565fa4ae57 /drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | |
| parent | 35d5f224a5593028ecbc784d7c6cb0c77fb3aac3 (diff) | |
| download | linux-1f928f51593ca07e2b125ca862fcff687e9e498b.tar.bz2 | |
drm/amdgpu: Use physical translation mode to access page table
On A+A platform, CPU write page directory and page table in cached
mode. So it is necessary for page table walker to snoop CPU cache.
This setting is necessary for page walker to snoop page directory
and page table data out of CPU cache.
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Acked-by: Christian Konig <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c index c3f3e755d4b7..08c50ce491e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c @@ -178,8 +178,17 @@ static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev) WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp); tmp = regVM_L2_CNTL4_DEFAULT; - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); - tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + if (adev->gmc.xgmi.connected_to_cpu) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 1); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + } else { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + } WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp); } |