diff options
| author | Huang Rui <ray.huang@amd.com> | 2022-05-18 22:05:03 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:44:15 -0400 |
| commit | 80d46fff373775fdea9917a7d13f6fb6fa5147ad (patch) | |
| tree | a7cf45e3c5640d1752fa636c5b3ba39efa43f13a /drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | |
| parent | 7101ab97e3b00ec1c68d09826bb0521d17783673 (diff) | |
| download | linux-80d46fff373775fdea9917a7d13f6fb6fa5147ad.tar.bz2 | |
drm/amdgpu: add apu sequence in the imu v11
APU required to issue the enable GFX IMU message after IMU reset.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/imu_v11_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index fd053158abbd..76383baa3929 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -24,6 +24,7 @@ #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_imu.h" +#include "amdgpu_dpm.h" #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" @@ -165,10 +166,10 @@ static int imu_v11_0_start(struct amdgpu_device *adev) imu_reg_val &= 0xfffffffe; WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val); - if (adev->gfx.imu.mode == DEBUG_MODE) - return imu_v11_0_wait_for_reset_status(adev); + if (adev->flags & AMD_IS_APU) + amdgpu_dpm_set_gfx_power_up_by_imu(adev); - return 0; + return imu_v11_0_wait_for_reset_status(adev); } static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] = |