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authorBorislav Petkov <borislav.petkov@amd.com>2009-10-16 13:39:30 +0200
committerBorislav Petkov <borislav.petkov@amd.com>2009-12-07 19:14:28 +0100
commit8de1d91e628c19c1154ca15b1ea1fcc0a098b793 (patch)
treea92a88f37eb18e02a65c1fc22cba918e73c962d9 /drivers/edac
parent68798e176012750fe8487bcfa0aa66fee21eae3c (diff)
downloadlinux-8de1d91e628c19c1154ca15b1ea1fcc0a098b793.tar.bz2
amd64_edac: cleanup rest of amd64_dump_misc_regs
Clarify bitfields description, add PCI config function/offset names to registers for easy reference, simplify code layout, remove unneeded info. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/amd64_edac.c33
1 files changed, 12 insertions, 21 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index cdda8d469cad..c65ad2d57e06 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -862,32 +862,23 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
amd64_dump_dramcfg_low(pvt->dclr0, 0);
- debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare);
+ debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
- if (boot_cpu_data.x86 == 0xf) {
- debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
- pvt->dhar, dhar_base(pvt->dhar),
- k8_dhar_offset(pvt->dhar));
- debugf1(" DramHoleValid=%s\n",
- (pvt->dhar & DHAR_VALID) ? "True" : "False");
+ debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, "
+ "offset: 0x%08x\n",
+ pvt->dhar,
+ dhar_base(pvt->dhar),
+ (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt->dhar)
+ : f10_dhar_offset(pvt->dhar));
- debugf1(" dbam-dkt: 0x%8.08x\n", pvt->dbam0);
+ debugf1(" DramHoleValid: %s\n",
+ (pvt->dhar & DHAR_VALID) ? "yes" : "no");
- /* everything below this point is Fam10h and above */
+ /* everything below this point is Fam10h and above */
+ if (boot_cpu_data.x86 == 0xf)
return;
- } else {
- debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n",
- pvt->dhar, dhar_base(pvt->dhar),
- f10_dhar_offset(pvt->dhar));
- debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n",
- (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) ?
- "True" : "False",
- (pvt->dhar & DHAR_VALID) ?
- "True" : "False");
- }
-
- /* Only if NOT ganged does dcl1 have valid info */
+ /* Only if NOT ganged does dclr1 have valid info */
if (!dct_ganging_enabled(pvt))
amd64_dump_dramcfg_low(pvt->dclr1, 1);