diff options
| author | Stefan Roese <sr@denx.de> | 2016-09-15 07:37:31 +0200 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2016-09-15 21:13:59 +0530 |
| commit | 77ff7a706f014a56d38f07acf220f381a8fe0fd8 (patch) | |
| tree | 060c52eedaba57d63912fc10e89bdefbfcb8ded1 /drivers/dma/mv_xor.h | |
| parent | 434cec62a6d73b8c8080cd992bc97a564fdd5a5a (diff) | |
| download | linux-77ff7a706f014a56d38f07acf220f381a8fe0fd8.tar.bz2 | |
dmaengine: mv_xor: Add support for IO (PCIe) src/dst areas
To enable the access to a specific area, the MVEBU XOR controllers needs
to have this area enabled / mapped via an address window. Right now,
only the DRAM memory area is enabled via such memory windows. So
using this driver to DMA to / from a e.g. PCIe memory region is
currently not supported.
This patch now adds support for such PCIe / IO regions by checking
if the src / dst address is located in an IO memory area in contrast
to being located in DRAM. This is done by using the newly introduced
MBus function mvebu_mbus_get_io_win_info(). If the src / dst address
is located in such an IO area, a new address window is created in
the XOR DMA controller. Enabling the controller to access this area.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Marcin Wojtas <mw@semihalf.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'drivers/dma/mv_xor.h')
| -rw-r--r-- | drivers/dma/mv_xor.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/dma/mv_xor.h b/drivers/dma/mv_xor.h index bf56e082e7cd..88eeab222a23 100644 --- a/drivers/dma/mv_xor.h +++ b/drivers/dma/mv_xor.h @@ -80,12 +80,17 @@ #define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2)) #define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2)) +#define WINDOW_COUNT 8 + struct mv_xor_device { void __iomem *xor_base; void __iomem *xor_high_base; struct clk *clk; struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS]; int xor_type; + + u32 win_start[WINDOW_COUNT]; + u32 win_end[WINDOW_COUNT]; }; /** @@ -127,6 +132,8 @@ struct mv_xor_chan { char dummy_dst[MV_XOR_MIN_BYTE_COUNT]; dma_addr_t dummy_src_addr, dummy_dst_addr; u32 saved_config_reg, saved_int_mask_reg; + + struct mv_xor_device *xordev; }; /** |