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authorBen Widawsky <ben.widawsky@intel.com>2022-02-01 13:28:53 -0800
committerDan Williams <dan.j.williams@intel.com>2022-02-08 22:57:30 -0800
commit4112a08dd3c5ea0a96029f14061f2320826cfd32 (patch)
treed2d8767ebb3d30d153ca69f26eae47802aba399b /drivers/cxl/pci.c
parent664bf115833c2d4ee717ab63f4e6e72a25c66e77 (diff)
downloadlinux-4112a08dd3c5ea0a96029f14061f2320826cfd32.tar.bz2
cxl/pci: Store component register base in cxlds
In preparation for defining a cxl_port object to represent the decoder resources of a memory expander capture the component register base address. The port driver uses the component register base to enumerate the HDM Decoder Capability structure. Unlike other cxl_port objects the endpoint port decodes from upstream SPA to downstream DPA rather than upstream port to downstream port. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> [djbw: clarify changelog] Link: https://lore.kernel.org/r/164375084181.484304.3919737667590006795.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/pci.c')
-rw-r--r--drivers/cxl/pci.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 8b435b875b65..bf14c365ea33 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -416,6 +416,17 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
+ /*
+ * If the component registers can't be found, the cxl_pci driver may
+ * still be useful for management functions so don't return an error.
+ */
+ cxlds->component_reg_phys = CXL_RESOURCE_NONE;
+ rc = cxl_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ if (rc)
+ dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
+
+ cxlds->component_reg_phys = cxl_regmap_to_base(pdev, &map);
+
rc = cxl_pci_setup_mailbox(cxlds);
if (rc)
return rc;