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| author | Dan Williams <dan.j.williams@intel.com> | 2022-05-18 16:34:37 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-05-19 08:50:41 -0700 |
| commit | 75b7ae29991f945b69c10d75b861d7d5e90bd541 (patch) | |
| tree | d373d2e53dea658a33c505278244c38bfea115a0 /drivers/cxl/cxlpci.h | |
| parent | 76a4121e86649bf381aa32cb69ede913def57202 (diff) | |
| download | linux-75b7ae29991f945b69c10d75b861d7d5e90bd541.tar.bz2 | |
cxl/mem: Validate port connectivity before dvsec ranges
In preparation for validating DVSEC ranges against the platform declared
CXL memory ranges (ACPI CFMWS) move port enumeration before the
endpoint's decoder validation. Ultimately this logic will move to the
port driver, but create a bisect point before that larger move.
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291687749.1426646.18091538443879226995.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/cxlpci.h')
0 files changed, 0 insertions, 0 deletions