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| author | Dave Jiang <dave.jiang@intel.com> | 2022-11-30 17:02:25 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-03 13:40:56 -0800 |
| commit | 6155ccc9ddf6642056f1c00c2851d1938d27a7f2 (patch) | |
| tree | 0e924b54ce76f8eb22ae38fbe97f63dd51bec593 /drivers/cxl/core/pci.c | |
| parent | 361187e04733eee19778ea9b01cb95a977c14c10 (diff) | |
| download | linux-6155ccc9ddf6642056f1c00c2851d1938d27a7f2.tar.bz2 | |
cxl/pci: Add callback to log AER correctable error
Add AER error handler callback to read the RAS capability structure
correctable error (CE) status register for the CXL device. Log the
error as a trace event and clear the error. For CXL devices, the driver
also needs to write back to the status register to clear the
unmasked correctable errors.
See CXL spec rev3.0 8.2.4.16 for RAS capability structure CE Status
Register.
Suggested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/166985287203.2871899.13605149073500556137.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl/core/pci.c')
0 files changed, 0 insertions, 0 deletions