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author | Thomas Gleixner <tglx@linutronix.de> | 2020-11-01 17:54:13 +0100 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2020-11-01 17:54:13 +0100 |
commit | 17bb415fefedb74d2ff02656cf59e4e3ab92ee20 (patch) | |
tree | 0ada27d370a1e2bfab1b57df9bb02a1a20371662 /drivers/clocksource/timer-riscv.c | |
parent | ceb2465c51195967f11f6507538579816ac67cb8 (diff) | |
parent | d95bdca75b3fb41bf185efe164e05aed820081a5 (diff) | |
download | linux-17bb415fefedb74d2ff02656cf59e4e3ab92ee20.tar.bz2 |
Merge tag 'irqchip-fixes-5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip fixes from Marc Zyngier:
- A couple of fixes after the IPI as IRQ patches (Kconfig, bcm2836)
- Two SiFive PLIC fixes (irq_set_affinity, hierarchy handling)
- "unmapped events" handling for the ti-sci-inta controller
- Tidying up for the irq-mst driver (static functions, Kconfig)
- Small cleanup in the Renesas irqpin driver
- STM32 exti can now handle LP timer events
Diffstat (limited to 'drivers/clocksource/timer-riscv.c')
-rw-r--r-- | drivers/clocksource/timer-riscv.c | 17 |
1 files changed, 2 insertions, 15 deletions
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 9de1dabfb126..c51c5ed15aa7 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -19,26 +19,13 @@ #include <linux/of_irq.h> #include <asm/smp.h> #include <asm/sbi.h> - -u64 __iomem *riscv_time_cmp; -u64 __iomem *riscv_time_val; - -static inline void mmio_set_timer(u64 val) -{ - void __iomem *r; - - r = riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()); - writeq_relaxed(val, r); -} +#include <asm/timex.h> static int riscv_clock_next_event(unsigned long delta, struct clock_event_device *ce) { csr_set(CSR_IE, IE_TIE); - if (IS_ENABLED(CONFIG_RISCV_SBI)) - sbi_set_timer(get_cycles64() + delta); - else - mmio_set_timer(get_cycles64() + delta); + sbi_set_timer(get_cycles64() + delta); return 0; } |