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authorThomas Gleixner <tglx@linutronix.de>2022-03-14 10:18:17 +0100
committerThomas Gleixner <tglx@linutronix.de>2022-03-14 10:18:17 +0100
commitb166e52541f2357ce126a92ce1d9a580fdca719d (patch)
tree11e440b630b14bdd32dc669940a95b5c564e495f /drivers/clocksource/arm_arch_timer.c
parent1f1893d78180c0c8bd4f53405420aa31eabfb263 (diff)
parent4467b8bad2401794fb89a0268c8c8257180bf60f (diff)
downloadlinux-b166e52541f2357ce126a92ce1d9a580fdca719d.tar.bz2
Merge tag 'timers-v5.18-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clocksource/events updates from Daniel Lezcano: - Fix return error code check for the timer-of layer when getting the base address (Guillaume Ranquet) - Remove MMIO dependency, add notrace annotation for sched_clock and increase the timer resolution for the Microchip PIT64b (Claudiu Beznea) - Convert DT bindings to yaml for the Tegra timer (David Heidelberg) - Fix compilation error on architecture other than ARM for the i.MX TPM (Nathan Chancellor) - Add support for the event stream scaling for 1GHz counter on the arch ARM timer (Marc Zyngier) - Support a higher number of interrupts by the Exynos MCT timer driver (Alim Akhtar) - Detect and prevent memory corruption when the specified number of interrupts in the DTS is greater than the array size in the code for the Exynos MCT timer (Krzysztof Kozlowski) - Fix regression from a previous errata fix on the TI DM timer (Drew Fustini) - Several fixes and code improvements for the i.MX TPM driver (Peng Fan) Link: https://lore.kernel.org/all/a8cd9be9-7d70-80df-2b74-1a8226a215e1@linaro.org
Diffstat (limited to 'drivers/clocksource/arm_arch_timer.c')
-rw-r--r--drivers/clocksource/arm_arch_timer.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 1ecd52f903b8..9ab8221ee3c6 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -880,10 +880,19 @@ static void __arch_timer_setup(unsigned type,
clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta);
}
-static void arch_timer_evtstrm_enable(int divider)
+static void arch_timer_evtstrm_enable(unsigned int divider)
{
u32 cntkctl = arch_timer_get_cntkctl();
+#ifdef CONFIG_ARM64
+ /* ECV is likely to require a large divider. Use the EVNTIS flag. */
+ if (cpus_have_const_cap(ARM64_HAS_ECV) && divider > 15) {
+ cntkctl |= ARCH_TIMER_EVT_INTERVAL_SCALE;
+ divider -= 8;
+ }
+#endif
+
+ divider = min(divider, 15U);
cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
/* Set the divider and enable virtual event stream */
cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
@@ -912,7 +921,7 @@ static void arch_timer_configure_evtstream(void)
lsb++;
/* enable event stream */
- arch_timer_evtstrm_enable(max(0, min(lsb, 15)));
+ arch_timer_evtstrm_enable(max(0, lsb));
}
static void arch_counter_set_user_access(void)