diff options
| author | Michael Turquette <mturquette@baylibre.com> | 2016-05-05 07:56:42 -0700 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2016-06-22 18:02:40 -0700 |
| commit | ab95d6e8ccd3a7514114d08f8b8e5ca0c303c412 (patch) | |
| tree | 75c91c59eb4f01d13fd871dc725ed28a636f0b12 /drivers/clk | |
| parent | 55d42c40dd8aa7384aa5c5295ef9037db2b00226 (diff) | |
| download | linux-ab95d6e8ccd3a7514114d08f8b8e5ca0c303c412.tar.bz2 | |
clk: meson8b: remove mali clk
This clock is undocumented and always orphaned. Get rid of it until we
have more complete clock tree documentation.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/meson/meson8b-clkc.c | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b-clkc.c index 94512b6ada25..dcd8f030782d 100644 --- a/drivers/clk/meson/meson8b-clkc.c +++ b/drivers/clk/meson/meson8b-clkc.c @@ -112,11 +112,8 @@ static const struct clk_div_table cpu_div_table[] = { }; PNAME(p_clk81) = { "fclk_div3", "fclk_div4", "fclk_div5" }; -PNAME(p_mali) = { "fclk_div3", "fclk_div4", "fclk_div5", - "fclk_div7", "zero" }; static u32 mux_table_clk81[] = { 6, 5, 7 }; -static u32 mux_table_mali[] = { 6, 5, 7, 4, 0 }; static const struct composite_conf clk81_conf __initconst = { .mux_table = mux_table_clk81, @@ -126,13 +123,6 @@ static const struct composite_conf clk81_conf __initconst = { .gate_parm = PARM(0x00, 7, 1), }; -static const struct composite_conf mali_conf __initconst = { - .mux_table = mux_table_mali, - .mux_parm = PARM(0x00, 9, 3), - .div_parm = PARM(0x00, 0, 7), - .gate_parm = PARM(0x00, 8, 1), -}; - static struct clk_fixed_rate meson8b_xtal = { .fixed_rate = 24000000, .hw.init = &(struct clk_init_data){ @@ -142,15 +132,6 @@ static struct clk_fixed_rate meson8b_xtal = { }, }; -static struct clk_fixed_rate meson8b_zero = { - .fixed_rate = 0, - .hw.init = &(struct clk_init_data){ - .name = "zero", - .num_parents = 0, - .ops = &clk_fixed_rate_ops, - }, -}; - static struct meson_clk_pll meson8b_fixed_pll = { .m = { .reg_off = MESON8B_REG_PLL_FIXED, @@ -301,8 +282,6 @@ static struct meson_clk_cpu meson8b_cpu_clk = { static const struct clk_conf meson8b_clk_confs[] __initconst = { COMPOSITE(MESON8B_REG_HHI_MPEG, CLKID_CLK81, "clk81", p_clk81, CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED, &clk81_conf), - COMPOSITE(MESON8B_REG_MALI, CLKID_MALI, "mali", p_mali, - CLK_IGNORE_UNUSED, &mali_conf), }; /* @@ -315,7 +294,6 @@ static const struct clk_conf meson8b_clk_confs[] __initconst = { static struct clk_hw_onecell_data meson8b_hw_onecell_data = { .hws = { [CLKID_XTAL] = &meson8b_xtal.hw, - [CLKID_ZERO] = &meson8b_zero.hw, [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw, [CLKID_PLL_VID] = &meson8b_vid_pll.hw, [CLKID_PLL_SYS] = &meson8b_sys_pll.hw, |