diff options
| author | Rahul Tanwar <rtanwar@maxlinear.com> | 2022-10-13 14:48:33 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-10-17 15:27:48 -0700 |
| commit | 106ef3bda21006fe37b62c85931230a6355d78d3 (patch) | |
| tree | 585a2f64153a6da107a0e1d8e3f39c6dbdecff96 /drivers/clk/x86/clk-cgu.c | |
| parent | a5d49bd369b8588c0ee9d4d0a2c0160558a3ab69 (diff) | |
| download | linux-106ef3bda21006fe37b62c85931230a6355d78d3.tar.bz2 | |
clk: mxl: Fix a clk entry by adding relevant flags
One of the clock entry "dcl" clk has some HW limitations. One is that
its rate can only by changed by changing its parent clk's rate & two is
that HW does not support enable/disable for this clk.
Handle above two limitations by adding relevant flags. Add standard flag
CLK_SET_RATE_PARENT to handle rate change and add driver internal flag
DIV_CLK_NO_MASK to handle enable/disable.
Fixes: d058fd9e8984 ("clk: intel: Add CGU clock driver for a new SoC")
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/a4770e7225f8a0c03c8ab2ba80434a4e8e9afb17.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/x86/clk-cgu.c')
| -rw-r--r-- | drivers/clk/x86/clk-cgu.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c index 4278a687076c..89b53f280aee 100644 --- a/drivers/clk/x86/clk-cgu.c +++ b/drivers/clk/x86/clk-cgu.c @@ -164,8 +164,9 @@ static int lgm_clk_divider_enable_disable(struct clk_hw *hw, int enable) { struct lgm_clk_divider *div = to_lgm_clk_divider(hw); - lgm_set_clk_val(div->membase, div->reg, div->shift_gate, - div->width_gate, enable); + if (div->flags != DIV_CLK_NO_MASK) + lgm_set_clk_val(div->membase, div->reg, div->shift_gate, + div->width_gate, enable); return 0; } |