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author | Olof Johansson <olof@lixom.net> | 2015-11-09 16:35:19 -0800 |
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committer | Olof Johansson <olof@lixom.net> | 2015-11-09 16:35:19 -0800 |
commit | 3e4dda70cc989a4f8079541972942609229e9f55 (patch) | |
tree | 0342db762349057fd2e1efb621ba265df187f1dc /drivers/clk/ti/clk-7xx.c | |
parent | 1b38b0e3349d733679e91b029a7f0dfd9e16a169 (diff) | |
parent | 8713181dced9b2d0c2a99613449b9e45b656df83 (diff) | |
download | linux-3e4dda70cc989a4f8079541972942609229e9f55.tar.bz2 |
Merge branch 'next/arm64' into next/dt
Merging in the few patches I had kept separate from main next/dt, since others
got merged here directly.
* next/arm64:
arm64: defconfig: Enable PCI generic host bridge by default
arm64: Juno: Add support for the PCIe host bridge on Juno R1
Documentation: of: Document the bindings used by Juno R1 PCIe host bridge
arm64: dts: mt8173: Add clocks for SCPSYS unit
arm64: dts: mt8173: Add subsystem clock controller device nodes
+ Linux 4.3-rc5
Diffstat (limited to 'drivers/clk/ti/clk-7xx.c')
-rw-r--r-- | drivers/clk/ti/clk-7xx.c | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index 9b5b289e6334..a911d7de3377 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -18,7 +18,6 @@ #include "clock.h" -#define DRA7_DPLL_ABE_DEFFREQ 180633600 #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 #define DRA7_DPLL_USB_DEFFREQ 960000000 @@ -313,27 +312,12 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *hdcp_ck; + struct clk *dpll_ck, *hdcp_ck; ti_dt_clocks_register(dra7xx_clks); omap2_clk_disable_autoidle_all(); - abe_dpll_mux = clk_get_sys(NULL, "abe_dpll_sys_clk_mux"); - sys_clkin2 = clk_get_sys(NULL, "sys_clkin2"); - dpll_ck = clk_get_sys(NULL, "dpll_abe_ck"); - - rc = clk_set_parent(abe_dpll_mux, sys_clkin2); - if (!rc) - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ); - if (rc) - pr_err("%s: failed to configure ABE DPLL!\n", __func__); - - dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck"); - rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2); - if (rc) - pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__); - dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck"); rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ); if (rc) |