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| author | Dmitry Osipenko <digetx@gmail.com> | 2021-05-16 19:30:40 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-05-31 15:16:46 +0200 |
| commit | 4782c0a5dd88e3797426e08c5c437e95a3156631 (patch) | |
| tree | 35496e4c64a046e6631a30a22bfe4b0d95acd783 /drivers/clk/tegra/clk-tegra30.c | |
| parent | 5d0f1c8ab10aee9934a418ddd7ec977b01ab2370 (diff) | |
| download | linux-4782c0a5dd88e3797426e08c5c437e95a3156631.tar.bz2 | |
clk: tegra: Don't deassert reset on enabling clocks
The Tegra clock driver contains legacy code which deasserts hardware reset
when peripheral clocks are enabled. This behaviour comes from a pre-CCF
era of the Tegra drivers. This is unacceptable for modern kernel drivers
which use generic CCF and reset-control APIs because it breaks assumptions
of the drivers about clk/reset sequences and about reset-propagation
delays. Hence remove the awkward legacy behaviour from the clk driver.
In particular PMC driver assumes that hardware blocks remains in reset
while power domain is turning on, but the clk driver deasserts the reset
before power clamp is removed, hence breaking the driver's assumption.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra30.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 5b6bd138be84..64121bc66d85 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1006,7 +1006,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = { TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0), TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1), TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2), - TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2), + TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, 0, TEGRA30_CLK_GR3D2), TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE), TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI), TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM), |