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authorStephen Warren <swarren@nvidia.com>2013-03-25 13:22:24 -0600
committerStephen Warren <swarren@nvidia.com>2013-04-04 16:09:05 -0600
commit441f199a37cfd66c5dd8dd45490bd3ea6971117d (patch)
tree0f7570e7985ea2b62f558e43d33caef6efa7e989 /drivers/clk/tegra/clk-tegra20.c
parent82ce742140f32394cc5be75f1c98cdbbff284582 (diff)
downloadlinux-441f199a37cfd66c5dd8dd45490bd3ea6971117d.tar.bz2
clk: tegra: defer application of init table
The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra20.c')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index a7dc0a937361..a15fb28197b5 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1252,6 +1252,11 @@ static __initdata struct tegra_clk_init_table init_table[] = {
{clk_max, clk_max, 0, 0}, /* This MUST be the last entry */
};
+static void __init tegra20_clock_apply_init_table(void)
+{
+ tegra_init_from_table(init_table, clks, clk_max);
+}
+
/*
* Some clocks may be used by different drivers depending on the board
* configuration. List those here to register them twice in the clock lookup
@@ -1318,7 +1323,7 @@ void __init tegra20_clock_init(struct device_node *np)
clk_data.clk_num = ARRAY_SIZE(clks);
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
- tegra_init_from_table(init_table, clks, clk_max);
+ tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
tegra_cpu_car_ops = &tegra20_cpu_car_ops;
}