diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2017-05-19 15:06:08 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-06-07 15:32:15 +0200 |
| commit | 13e0dde8b2ed043aa3e65437342d501715d975c1 (patch) | |
| tree | ebc8e171a82bb4743fbcc27de067fcf79a261046 /drivers/clk/sunxi-ng/ccu-sun8i-r.c | |
| parent | 11ad470c5486ab848f04418c56d58f078ad53a9a (diff) | |
| download | linux-13e0dde8b2ed043aa3e65437342d501715d975c1.tar.bz2 | |
clk: sunxi-ng: Support multiple variable pre-dividers
On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.
As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun8i-r.c')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun8i-r.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c index 119f47b568ea..de02be75785c 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c @@ -27,6 +27,9 @@ static const char * const ar100_parents[] = { "osc32k", "osc24M", "pll-periph0", "iosc" }; +static const struct ccu_mux_var_prediv ar100_predivs[] = { + { .index = 2, .shift = 8, .width = 5 }, +}; static struct ccu_div ar100_clk = { .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), @@ -35,11 +38,8 @@ static struct ccu_div ar100_clk = { .shift = 16, .width = 2, - .variable_prediv = { - .index = 2, - .shift = 8, - .width = 5, - }, + .var_predivs = ar100_predivs, + .n_var_predivs = ARRAY_SIZE(ar100_predivs), }, .common = { |