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authorChen-Yu Tsai <wens@csie.org>2017-02-14 10:23:32 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-03-06 07:36:04 +0100
commit9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d (patch)
treec3f90202a217ea625f2c534142bb15782bbae4bc /drivers/clk/sunxi-ng/ccu-sun6i-a31.c
parent69c9ae5041309553472ee798d7683be31bcdc434 (diff)
downloadlinux-9ad0bb39fce319d7b92c17d306ed0a9f70a02e7d.tar.bz2
clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock
The enable bit offset for the hdmi-ddc module clock is wrong. It is pointing to the main hdmi module clock enable bit. Reported-by: Bob Ham <rah@settrans.net> Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks") Cc: stable@vger.kernel.org # 4.9.x- Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun6i-a31.c')
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun6i-a31.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 4c9a920ff4ab..89e68d29bf45 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -608,7 +608,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
0x150, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
-static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0);
+static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);