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author | Zong Li <zong.li@sifive.com> | 2022-03-04 18:03:21 +0800 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2022-03-15 15:56:28 -0700 |
commit | 5e916932df639bc2eeecc96c3a1f2cce496f1a93 (patch) | |
tree | 08629a87b765010731a5b9b555746f816d9202a5 /drivers/clk/sifive/fu740-prci.c | |
parent | 24a4a29f755e457d5485c5d9a1006be560ae48ce (diff) | |
download | linux-5e916932df639bc2eeecc96c3a1f2cce496f1a93.tar.bz2 |
clk: sifive: Move all stuff into SoCs header files from C files
Improve PRCI driver to reduce the complexity, we remove the SoCs C files
by putting all stuff in each SoCs header files, and include these
SoCs-specific header files in core of PRCI. It can also avoid the W=1
kernel build warnings about variable defined but not used
[-Wunused-const-variable=], like commit 487dc7bb6a0c ("clk: sifive:
fu540-prci: Declare static const variable 'prci_clk_fu540' where it's
used") does.
Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/a3c7ec5c46c1d8be455d1c347db4855bb56cec53.1646388139.git.zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/sifive/fu740-prci.c')
-rw-r--r-- | drivers/clk/sifive/fu740-prci.c | 133 |
1 files changed, 0 insertions, 133 deletions
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c deleted file mode 100644 index f27d1a42d946..000000000000 --- a/drivers/clk/sifive/fu740-prci.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020-2022 SiFive, Inc. - * Copyright (C) 2020-2022 Zong Li - */ - -#include <linux/module.h> - -#include <dt-bindings/clock/sifive-fu740-prci.h> - -#include "sifive-prci.h" - -/* PRCI integration data for each WRPLL instance */ - -static struct __prci_wrpll_data sifive_fu740_prci_corepll_data = { - .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, - .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_coreclksel_use_hfclk, - .disable_bypass = sifive_prci_coreclksel_use_final_corepll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data = { - .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, - .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data = { - .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, - .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data = { - .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, - .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_corepllsel_use_corepll, - .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data = { - .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, - .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, - .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, - .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data = { - .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, - .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, -}; - -/* Linux clock framework integration */ - -static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = { - .set_rate = sifive_prci_wrpll_set_rate, - .round_rate = sifive_prci_wrpll_round_rate, - .recalc_rate = sifive_prci_wrpll_recalc_rate, - .enable = sifive_prci_clock_enable, - .disable = sifive_prci_clock_disable, - .is_enabled = sifive_clk_is_enabled, -}; - -static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = { - .recalc_rate = sifive_prci_wrpll_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = { - .recalc_rate = sifive_prci_tlclksel_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { - .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = { - .enable = sifive_prci_pcie_aux_clock_enable, - .disable = sifive_prci_pcie_aux_clock_disable, - .is_enabled = sifive_prci_pcie_aux_clock_is_enabled, -}; - -/* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] = { - [FU740_PRCI_CLK_COREPLL] = { - .name = "corepll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_corepll_data, - }, - [FU740_PRCI_CLK_DDRPLL] = { - .name = "ddrpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_ro_clk_ops, - .pwd = &sifive_fu740_prci_ddrpll_data, - }, - [FU740_PRCI_CLK_GEMGXLPLL] = { - .name = "gemgxlpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_gemgxlpll_data, - }, - [FU740_PRCI_CLK_DVFSCOREPLL] = { - .name = "dvfscorepll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_dvfscorepll_data, - }, - [FU740_PRCI_CLK_HFPCLKPLL] = { - .name = "hfpclkpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_hfpclkpll_data, - }, - [FU740_PRCI_CLK_CLTXPLL] = { - .name = "cltxpll", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_wrpll_clk_ops, - .pwd = &sifive_fu740_prci_cltxpll_data, - }, - [FU740_PRCI_CLK_TLCLK] = { - .name = "tlclk", - .parent_name = "corepll", - .ops = &sifive_fu740_prci_tlclksel_clk_ops, - }, - [FU740_PRCI_CLK_PCLK] = { - .name = "pclk", - .parent_name = "hfpclkpll", - .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, - }, - [FU740_PRCI_CLK_PCIE_AUX] = { - .name = "pcie_aux", - .parent_name = "hfclk", - .ops = &sifive_fu740_prci_pcie_aux_clk_ops, - }, -}; |