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| author | Alim Akhtar <alim.akhtar@samsung.com> | 2015-08-26 09:00:43 +0530 |
|---|---|---|
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2015-09-15 11:00:08 +0200 |
| commit | 7cca2e0744a990bfa0ae93a40c886fd589fb37b7 (patch) | |
| tree | 6f76869da28053596796dd69a812b6b8ba1214c2 /drivers/clk/samsung/clk-exynos7.c | |
| parent | cfc7588a310254b659cb0a6fcca1fffd3f223090 (diff) | |
| download | linux-7cca2e0744a990bfa0ae93a40c886fd589fb37b7.tar.bz2 | |
clk: samsung: exynos7: Correct nr_clk_ids for fsys0
This patch corrects the nr_clk_ids for fsys0 block
which is wrongly set to number of clocks of the TOP1 CMU.
This also adjusts the gate clocks order.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos7.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos7.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index b5706fecdb21..db85446c4467 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -846,13 +846,13 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = { }; static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { - GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", - "mout_aclk_fsys0_200_user", - ENABLE_ACLK_FSYS00, 19, 0, 0), GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 3, 0, 0), GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 4, 0, 0), + GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", + "mout_aclk_fsys0_200_user", + ENABLE_ACLK_FSYS00, 19, 0, 0), GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS01, 29, 0, 0), @@ -884,7 +884,7 @@ static struct samsung_cmu_info fsys0_cmu_info __initdata = { .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), .gate_clks = fsys0_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), - .nr_clk_ids = TOP1_NR_CLK, + .nr_clk_ids = FSYS0_NR_CLK, .clk_regs = fsys0_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), }; |