diff options
| author | Ryo Kodama <ryo.kodama.vz@renesas.com> | 2017-04-20 02:46:38 +0900 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-05-15 09:46:31 +0200 |
| commit | a0b381fafffaf07c939524c7708a270023d1ad95 (patch) | |
| tree | 00c49e8bcf9f89a7c1ae6a3245463a40be9fe08a /drivers/clk/renesas/r8a7796-cpg-mssr.c | |
| parent | a703e11f41ee7855a711764443056519fc71a78e (diff) | |
| download | linux-a0b381fafffaf07c939524c7708a270023d1ad95.tar.bz2 | |
clk: renesas: r8a7796: Add PWM clock
This patch adds PWM clock for PWM.
Signed-off-by: Ryo Kodama <ryo.kodama.vz@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
[geert: Correct parent clock]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a7796-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 5c95e636a8d6..ab8ad5e6f537 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -156,6 +156,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { DEF_MOD("hscif1", 519, R8A7796_CLK_S3D1), DEF_MOD("hscif0", 520, R8A7796_CLK_S3D1), DEF_MOD("thermal", 522, R8A7796_CLK_CP), + DEF_MOD("pwm", 523, R8A7796_CLK_S0D12), DEF_MOD("fcpvd2", 601, R8A7796_CLK_S0D2), DEF_MOD("fcpvd1", 602, R8A7796_CLK_S0D2), DEF_MOD("fcpvd0", 603, R8A7796_CLK_S0D2), |