diff options
| author | Robert Foss <robert.foss@linaro.org> | 2022-11-02 10:01:36 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2022-11-05 23:38:18 -0500 |
| commit | b5f84650fb0d6ebaa48a5f99183de70d32d0b115 (patch) | |
| tree | 26bbfb11f4b7e1a51bc3eb33639f0107d8ef0129 /drivers/clk/qcom | |
| parent | ac1c5a03d3772b1db25e8092f771aa33f6ae2f7e (diff) | |
| download | linux-b5f84650fb0d6ebaa48a5f99183de70d32d0b115.tar.bz2 | |
clk: qcom: dispcc-sm8250: Disable EDP_GTC for sm8350
SM8350 does not have the EDP_GTC clock, so let's disable it
for this SoC.
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-2-robert.foss@linaro.org
Diffstat (limited to 'drivers/clk/qcom')
| -rw-r--r-- | drivers/clk/qcom/dispcc-sm8250.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 709076f0f9d7..180ac2726f7e 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -1330,6 +1330,9 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; disp_cc_pll1.vco_table = lucid_5lpe_vco; + + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL; + disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL; } clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); |