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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2020-04-17 20:41:24 +0200
committerJerome Brunet <jbrunet@baylibre.com>2020-04-29 10:26:53 +0200
commitda1978ac3d6cf278dedf5edbf350445a0fff2f08 (patch)
treea9b83d34f20dbf56db0ea9a8e9addb65f9c11800 /drivers/clk/meson
parent6dde0ae30a9a883778154f8377ed50a2c7752211 (diff)
downloadlinux-da1978ac3d6cf278dedf5edbf350445a0fff2f08.tar.bz2
clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not easy to see that the vendor kernel does the same, but it actually does. meson_clk_pll_ops in mainline still cannot fully recalculate all rates from the HDMI PLL registers because some register bits (at the time of writing it's unknown which bits are used for this) double the HDMI PLL output rate (compared to simply considering M, N and FRAC) for some (but not all) PLL settings. Update the vid_pll_in_sel parent so our clock calculation works for simple clock settings like the CVBS output (where no rate doubling is going on). The PLL ops need to be fixed later on for more complex clock settings (all HDMI rates). Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees") Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-2-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/clk/meson')
-rw-r--r--drivers/clk/meson/meson8b.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 7c55c695cbae..90d284ffc780 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1077,7 +1077,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
* Meson8m2: vid2_pll
*/
.parent_hws = (const struct clk_hw *[]) {
- &meson8b_hdmi_pll_dco.hw
+ &meson8b_hdmi_pll_lvds_out.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,