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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-09-27 10:59:21 +0200 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-11-23 15:11:57 +0100 |
| commit | a8662eadd1032018f31e37deda811790b2326662 (patch) | |
| tree | 25599a906552c2e421780239d40e40e9fe45d3cd /drivers/clk/meson/meson8b.c | |
| parent | ad9b2b8e53af61375322e3c7d624acf3a3ef53b0 (diff) | |
| download | linux-a8662eadd1032018f31e37deda811790b2326662.tar.bz2 | |
clk: meson: meson8b: fix the width of the cpu_scale_div clock
According to the public S805 datasheet HHI_SYS_CPU_CLK_CNTL1[29:20] is
the register for the CPU scale_div clock. This matches the code in
Amlogic's 3.10 GPL kernel sources:
N = (aml_read_reg32(P_HHI_SYS_CPU_CLK_CNTL1) >> 20) & 0x3FF;
This means that the divider register is 10 bit wide instead of 9 bits.
So far this is not a problem since all u-boot versions I have seen are
not using the cpu_scale_div clock at all (instead they are configuring
the CPU clock to run off cpu_in_sel directly).
The fixes tag points to the latest rework of the CPU clocks. However,
even before the rework it was wrong. Commit 7a29a869434e8b ("clk: meson:
Add support for Meson clock controller") defines MESON_N_WIDTH as 9 (in
drivers/clk/meson/clk-cpu.c). But since the old clk-cpu implementation
this only carries the fixes tag for the CPU clock rewordk.
Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20180927085921.24627-3-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/clk/meson/meson8b.c')
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index badf7a2ae70d..9bd5920da0ff 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -595,7 +595,7 @@ static struct clk_regmap meson8b_cpu_scale_div = { .data = &(struct clk_regmap_div_data){ .offset = HHI_SYS_CPU_CLK_CNTL1, .shift = 20, - .width = 9, + .width = 10, .table = cpu_scale_table, .flags = CLK_DIVIDER_ALLOW_ZERO, }, |