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| author | Neil Armstrong <narmstrong@baylibre.com> | 2019-08-26 09:25:38 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2019-08-26 11:04:54 +0200 |
| commit | da3ceae4ec9f581a50dc0763710078f22d3bc72a (patch) | |
| tree | b87b8907e060e3cac59089181c378071c3ca1add /drivers/clk/meson/g12a.h | |
| parent | 2edccd319fdef9bc35c06fe4150b21099ac99579 (diff) | |
| download | linux-da3ceae4ec9f581a50dc0763710078f22d3bc72a.tar.bz2 | |
clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.
But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.
They are set read-only because the early boot stages sets them to select
the CPU0 input clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/g12a.h')
| -rw-r--r-- | drivers/clk/meson/g12a.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h index 6804fcced6b5..9df4068aced1 100644 --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h @@ -256,7 +256,7 @@ #define CLKID_DSU_CLK_DYN 250 #define CLKID_DSU_CLK_FINAL 251 -#define NR_CLKS 253 +#define NR_CLKS 256 /* include the CLKIDs that have been made part of the DT binding */ #include <dt-bindings/clock/g12a-clkc.h> |