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author | Rex Zhu <Rex.Zhu@amd.com> | 2018-04-18 18:46:07 +0800 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2018-05-15 13:43:52 -0500 |
commit | c5a4484941be553b37facd681daf990d040cce81 (patch) | |
tree | 17edddfbb8a7dcfab0eb3bdf3c47336b5cc43634 /drivers/clk/loongson1 | |
parent | ba9ca0886dc0541ac1a716b3cbd43f640a1ce8c4 (diff) | |
download | linux-c5a4484941be553b37facd681daf990d040cce81.tar.bz2 |
drm/amd/pp: Add OVERDRIVE support on Vega10 (v2)
when bit14 in module parameter ppfeaturemask was set.
od feature will be enabled on Vega10 except vbios not support.
user can read od range by reading sysfs pp_od_clk_voltage,
cat pp_od_clk_voltage
OD_SCLK:
0: 852Mhz 800mV
1: 991Mhz 900mV
2: 1138Mhz 950mV
3: 1269Mhz 1000mV
4: 1348Mhz 1050mV
5: 1399Mhz 1100mV
6: 1440Mhz 1150mV
7: 1500Mhz 1200mV
OD_MCLK:
0: 167Mhz 800mV
1: 500Mhz 800mV
2: 800Mhz 950mV
3: 945Mhz 1000mV
OD_RANGE:
SCLK: 852MHz 2200MHz
MCLK: 167MHz 1500MHz
VDDC: 800mV 1200mV
and can configure the clock/voltage by writing pp_od_clk_voltage
for example:
echo "s 0 900 820">pp_od_clk_voltage to change the sclk/vddc
to 900MHz and 820 mV in dpm level0.
echo "r" to change the clk/voltage to default value.
echo "c">pp_od_clk_voltage
to commit the change
v2: squash in warning fix (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/clk/loongson1')
0 files changed, 0 insertions, 0 deletions