diff options
| author | Peng Fan <peng.fan@nxp.com> | 2022-02-28 10:09:07 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2022-03-04 17:06:29 +0200 |
| commit | 1b26cb8a77a49d8f8b5b723ef1db4cd6d2434dfc (patch) | |
| tree | 1309e2aad70fa820253fc2c0a1473d6e2a14de53 /drivers/clk/imx/clk.h | |
| parent | 11994196178d9038d659c2b9468d7c219b708a37 (diff) | |
| download | linux-1b26cb8a77a49d8f8b5b723ef1db4cd6d2434dfc.tar.bz2 | |
clk: imx: support fracn gppll
This PLL module is a Fractional-N synthesizer,
supporting 30-bit numerator and denominator. Numerator is a signed
number. It has feature to adjust fractional portion of feedback
divider dynamically. This fracn gppll is used in i.MX93.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20220228020908.2810346-5-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'drivers/clk/imx/clk.h')
| -rw-r--r-- | drivers/clk/imx/clk.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 63eb7c53b123..a7cbbcd1a3f4 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -72,6 +72,27 @@ extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; +/* NOTE: Rate table should be kept sorted in descending order. */ +struct imx_fracn_gppll_rate_table { + unsigned int rate; + unsigned int mfi; + unsigned int mfn; + unsigned int mfd; + unsigned int rdiv; + unsigned int odiv; +}; + +struct imx_fracn_gppll_clk { + const struct imx_fracn_gppll_rate_table *rate_table; + int rate_count; + int flags; +}; + +struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk); + +extern struct imx_fracn_gppll_clk imx_fracn_gppll; + #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)) |