diff options
author | Peng Fan <peng.fan@nxp.com> | 2022-02-28 20:41:11 +0800 |
---|---|---|
committer | Abel Vesa <abel.vesa@nxp.com> | 2022-04-12 11:17:43 +0300 |
commit | 19565ea12d61c69ef2be97a97b426ba5c55572ff (patch) | |
tree | 8ba2366a7be9a8f5103037f2ac95db1e78bd7dc3 /drivers/clk/imx/clk.h | |
parent | cdc86e473b353c8a026a337ee9fb9e1fbbe2276b (diff) | |
download | linux-19565ea12d61c69ef2be97a97b426ba5c55572ff.tar.bz2 |
clk: imx: add mcore_booted module paratemter
Add mcore_booted boot parameter which could simplify AMP clock
management. To i.MX8M, there is CCM(clock control Module) to generate
clock root clock, anatop(analog PLL module) to generate PLL, and CCGR
(clock gating) to gate clocks to peripherals. As below:
anatop->ccm->ccgr->peripheral
Linux handles the clock management and the auxiliary core is under
control of Linux. Although there is per hardware domain control for CCGR
and CCM, auxiliary core normally only use CCGR hardware domain control
to avoid linux gate off the clk to peripherals and leave CCM ana anatop
to Linux.
Per NXP hardware design, because CCGR already support gate to
peripherals, and clk root gate power leakage is negligible. So
when in AMP case, we could not register the clk root gate.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220228124112.3974242-1-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Diffstat (limited to 'drivers/clk/imx/clk.h')
-rw-r--r-- | drivers/clk/imx/clk.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index a7cbbcd1a3f4..5061a06468df 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -7,6 +7,7 @@ #include <linux/clk-provider.h> extern spinlock_t imx_ccm_lock; +extern bool mcore_booted; void imx_check_clocks(struct clk *clks[], unsigned int count); void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); |