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authorStephen Boyd <sboyd@kernel.org>2021-09-01 15:25:15 -0700
committerStephen Boyd <sboyd@kernel.org>2021-09-01 15:25:15 -0700
commit7110569a096d820876f99543660741bd8a96af7c (patch)
tree431e711bdc7284da146f916c0050cb0cc64d8a94 /drivers/clk/clk-milbeaut.c
parent4990d8c1333dc827aff8f18ff616bec4e9a32e2d (diff)
parenta1cde1f0172eefe55c97310b27aca2076fdaff01 (diff)
parent28fc39f7abecaed2f4633cd5fd3775b8031dffde (diff)
parent23a57ee7af01a51cf5e8568f3410dd493ecb8d3d (diff)
downloadlinux-7110569a096d820876f99543660741bd8a96af7c.tar.bz2
Merge branches 'clk-renesas', 'clk-cleanup' and 'clk-determine-divider' into clk-next
- Migrate some clk drivers to clk_divider_ops.determine_rate * clk-renesas: clk: renesas: Make CLK_R9A06G032 invisible clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2 dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock clk: renesas: r9a07g044: Add clock and reset entries for ADC clk: renesas: r9a07g044: Add clock and reset entries for CANFD clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] clk: renesas: r9a07g044: Add GPIO clock and reset entries clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries clk: renesas: r9a07g044: Add USB clocks/resets clk: renesas: r9a07g044: Add DMAC clocks/resets clk: renesas: r9a07g044: Add I2C clocks/resets clk: renesas: r8a779a0: Add the DSI clocks clk: renesas: r8a779a0: Add the DU clock clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() clk: renesas: rzg2l: Avoid mixing error pointers and NULL clk: renesas: rzg2l: Fix a double free on error clk: renesas: rzg2l: Fix return value and unused assignment clk: renesas: rzg2l: Remove unneeded semicolon * clk-cleanup: clk: palmas: Add a missing SPDX license header clk: Align provider-specific CLK_* bit definitions * clk-determine-divider: clk: stm32mp1: Switch to clk_divider.determine_rate clk: stm32h7: Switch to clk_divider.determine_rate clk: stm32f4: Switch to clk_divider.determine_rate clk: bcm2835: Switch to clk_divider.determine_rate clk: divider: Implement and wire up .determine_rate by default