diff options
author | Jon Mason <jonmason@broadcom.com> | 2015-10-15 15:48:28 -0400 |
---|---|---|
committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-10-21 17:02:14 -0700 |
commit | 7968d24107f5a50a11792f8a7f011877e7470dfa (patch) | |
tree | 06e00e12d1b5cf4a76c12b38a6295944594f043b /drivers/clk/bcm/clk-iproc-pll.c | |
parent | 5f024b0685f753325f1b8cacbe37ffe5921b13d1 (diff) | |
download | linux-7968d24107f5a50a11792f8a7f011877e7470dfa.tar.bz2 |
clk: iproc: Add PLL base write function
All writes to the PLL base address must be flushed if the
IPROC_CLK_NEEDS_READ_BACK flag is set. If we add a function to make the
necessary write and reads, we can make sure that any future code which
makes PLL base writes will do the correct thing.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/bcm/clk-iproc-pll.c')
-rw-r--r-- | drivers/clk/bcm/clk-iproc-pll.c | 80 |
1 files changed, 33 insertions, 47 deletions
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c index e27acb9c655c..bfa28ba1394e 100644 --- a/drivers/clk/bcm/clk-iproc-pll.c +++ b/drivers/clk/bcm/clk-iproc-pll.c @@ -137,6 +137,18 @@ static int pll_wait_for_lock(struct iproc_pll *pll) return -EIO; } +static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, + const u32 offset, u32 val) +{ + const struct iproc_pll_ctrl *ctrl = pll->ctrl; + + writel(val, base + offset); + + if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && + base == pll->pll_base)) + val = readl(base + offset); +} + static void __pll_disable(struct iproc_pll *pll) { const struct iproc_pll_ctrl *ctrl = pll->ctrl; @@ -145,27 +157,24 @@ static void __pll_disable(struct iproc_pll *pll) if (ctrl->flags & IPROC_CLK_PLL_ASIU) { val = readl(pll->asiu_base + ctrl->asiu.offset); val &= ~(1 << ctrl->asiu.en_shift); - writel(val, pll->asiu_base + ctrl->asiu.offset); + iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); } if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { val = readl(pll->pll_base + ctrl->aon.offset); val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; - writel(val, pll->pll_base + ctrl->aon.offset); - - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->aon.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); } if (pll->pwr_base) { /* latch input value so core power can be shut down */ val = readl(pll->pwr_base + ctrl->aon.offset); val |= 1 << ctrl->aon.iso_shift; - writel(val, pll->pwr_base + ctrl->aon.offset); + iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); /* power down the core */ val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); - writel(val, pll->pwr_base + ctrl->aon.offset); + iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); } } @@ -177,10 +186,7 @@ static int __pll_enable(struct iproc_pll *pll) if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { val = readl(pll->pll_base + ctrl->aon.offset); val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); - writel(val, pll->pll_base + ctrl->aon.offset); - - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->aon.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->aon.offset, val); } if (pll->pwr_base) { @@ -188,14 +194,14 @@ static int __pll_enable(struct iproc_pll *pll) val = readl(pll->pwr_base + ctrl->aon.offset); val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; val &= ~(1 << ctrl->aon.iso_shift); - writel(val, pll->pwr_base + ctrl->aon.offset); + iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); } /* certain PLLs also need to be ungated from the ASIU top level */ if (ctrl->flags & IPROC_CLK_PLL_ASIU) { val = readl(pll->asiu_base + ctrl->asiu.offset); val |= (1 << ctrl->asiu.en_shift); - writel(val, pll->asiu_base + ctrl->asiu.offset); + iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); } return 0; @@ -209,9 +215,7 @@ static void __pll_put_in_reset(struct iproc_pll *pll) val = readl(pll->pll_base + reset->offset); val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift); - writel(val, pll->pll_base + reset->offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + reset->offset); + iproc_pll_write(pll, pll->pll_base, reset->offset, val); } static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, @@ -228,9 +232,7 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, val |= ki << reset->ki_shift | kp << reset->kp_shift | ka << reset->ka_shift; val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; - writel(val, pll->pll_base + reset->offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + reset->offset); + iproc_pll_write(pll, pll->pll_base, reset->offset, val); } static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, @@ -285,9 +287,8 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, /* put PLL in reset */ __pll_put_in_reset(pll); - writel(0, pll->pll_base + ctrl->vco_ctrl.u_offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->vco_ctrl.u_offset); + iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.u_offset, 0); + val = readl(pll->pll_base + ctrl->vco_ctrl.l_offset); if (rate >= VCO_LOW && rate < VCO_MID) @@ -298,17 +299,13 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, else val |= (1 << PLL_VCO_HIGH_SHIFT); - writel(val, pll->pll_base + ctrl->vco_ctrl.l_offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->vco_ctrl.l_offset); + iproc_pll_write(pll, pll->pll_base, ctrl->vco_ctrl.l_offset, val); /* program integer part of NDIV */ val = readl(pll->pll_base + ctrl->ndiv_int.offset); val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); val |= vco->ndiv_int << ctrl->ndiv_int.shift; - writel(val, pll->pll_base + ctrl->ndiv_int.offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->ndiv_int.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_int.offset, val); /* program fractional part of NDIV */ if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { @@ -316,18 +313,15 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, val &= ~(bit_mask(ctrl->ndiv_frac.width) << ctrl->ndiv_frac.shift); val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; - writel(val, pll->pll_base + ctrl->ndiv_frac.offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->ndiv_frac.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->ndiv_frac.offset, + val); } /* program PDIV */ val = readl(pll->pll_base + ctrl->pdiv.offset); val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); val |= vco->pdiv << ctrl->pdiv.shift; - writel(val, pll->pll_base + ctrl->pdiv.offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->pdiv.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->pdiv.offset, val); __pll_bring_out_reset(pll, kp, ka, ki); @@ -467,14 +461,12 @@ static int iproc_clk_enable(struct clk_hw *hw) /* channel enable is active low */ val = readl(pll->pll_base + ctrl->enable.offset); val &= ~(1 << ctrl->enable.enable_shift); - writel(val, pll->pll_base + ctrl->enable.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); /* also make sure channel is not held */ val = readl(pll->pll_base + ctrl->enable.offset); val &= ~(1 << ctrl->enable.hold_shift); - writel(val, pll->pll_base + ctrl->enable.offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->enable.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); return 0; } @@ -491,9 +483,7 @@ static void iproc_clk_disable(struct clk_hw *hw) val = readl(pll->pll_base + ctrl->enable.offset); val |= 1 << ctrl->enable.enable_shift; - writel(val, pll->pll_base + ctrl->enable.offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->enable.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->enable.offset, val); } static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, @@ -562,9 +552,7 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate, val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); val |= div << ctrl->mdiv.shift; } - writel(val, pll->pll_base + ctrl->mdiv.offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->mdiv.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->mdiv.offset, val); clk->rate = parent_rate / div; return 0; @@ -591,9 +579,7 @@ static void iproc_pll_sw_cfg(struct iproc_pll *pll) val = readl(pll->pll_base + ctrl->sw_ctrl.offset); val |= BIT(ctrl->sw_ctrl.shift); - writel(val, pll->pll_base + ctrl->sw_ctrl.offset); - if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK)) - readl(pll->pll_base + ctrl->sw_ctrl.offset); + iproc_pll_write(pll, pll->pll_base, ctrl->sw_ctrl.offset, val); } } |