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| author | Taimur Hassan <syed.hassan@amd.com> | 2020-10-04 15:20:45 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-10-26 13:29:21 -0400 |
| commit | a47cc3ab051f963ebca820dc48e887e9a7101244 (patch) | |
| tree | 91532e3d3d0e7b34fc0fa38ef05e6d6dafa1cd6d /crypto/camellia_generic.c | |
| parent | 1db522cd03fdf692047e2317cfa16cf89bd42992 (diff) | |
| download | linux-a47cc3ab051f963ebca820dc48e887e9a7101244.tar.bz2 | |
drm/amd/display: Raise DPG height during timing synchronization
[Why]
Underflow counter increases in AGM when performing some mode switches due
to timing sync, which is a known hardware issue.
[How]
Temporarily raise DPG height during timing sync so that underflow is not
reported.
Signed-off-by: Taimur Hassan <syed.hassan@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'crypto/camellia_generic.c')
0 files changed, 0 insertions, 0 deletions