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| author | Sreekanth Reddy <sreekanth.reddy@broadcom.com> | 2019-06-24 10:42:56 -0400 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2019-06-26 22:58:34 -0400 |
| commit | eedc42a074de55a0164e722d5ca2ec4bd397b8bc (patch) | |
| tree | 85670b7d26ed0ac1fc807aaf0b7c4c9752ca530e /crypto/adiantum.c | |
| parent | 610ef1e955cd262a5f72d8401a36c9cfca6072fe (diff) | |
| download | linux-eedc42a074de55a0164e722d5ca2ec4bd397b8bc.tar.bz2 | |
scsi: mpt3sas: Fix msix load balance on and off settings
Enable msix load balance only when combined reply queue mode is disabled on
the SAS3 and above generation HBA devices.
Earlier msix load balance used to enable if the number of online cpus is
greater than the number of MSI-X vectors enabled on the HBA. Combined reply
queue mode will be disabled only on those HBA which works in shared
resources mode. I.e. on SAS3 HBAs it will be <= 8 and on SAS35 HBA devices
it will be <= 16.
- Before this patch if system has 256 logical CPUs and HBA exposes 128
MSI-X vectors, driver will enable msix load balance.
- After this patch if system has 256 logical CPUs and HBA exposes 128
MSI-X vectors, driver will disable msix load balance.
- After this patch if system has 256 logical CPUs and HBA exposes 16 MSI-X
vectors (due to combined reply queue mode being off in HW), driver will
enable msix load balance.
Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'crypto/adiantum.c')
0 files changed, 0 insertions, 0 deletions